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Add vivado vlog support#100

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Rename "xvhdl" builder to "xsim"
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Arne Kreddig committedJan 26, 2023
commit78c6610746f386f85f4e93f9c07d549f19ebd28d
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Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
builder =xvhdl
builder =xsim

target_dir = .build
vhdl basic_library basic_library/very_common_pkg.vhd
Expand All@@ -7,5 +7,5 @@ vhdl basic_library basic_library/clock_divider.vhd
vhdl another_library another_library/foo.vhd
vhdl basic_library basic_library/package_with_functions.vhd
vhdl basic_library basic_library/clk_en_generator.vhd
vhdlbasic_library basic_library/two_entities_one_file.vhd
vhdlbasic_library basic_library/use_entity_a_and_b.vhd
vhdl basic_library basic_library/two_entities_one_file.vhd
vhdl basic_library basic_library/use_entity_a_and_b.vhd
14 changes: 7 additions & 7 deletionshdl_checker/builder_utils.py
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Expand Up@@ -34,7 +34,7 @@
from .builders.fallback import Fallback
from .builders.ghdl import GHDL
from .builders.msim import MSim
from .builders.xvhdl importXVHDL
from .builders.xsim importXSIM

from hdl_checker.parser_utils import findRtlSourcesByPath
from hdl_checker.parsers.elements.identifier import Identifier
Expand All@@ -56,7 +56,7 @@

_logger = logging.getLogger(__name__)

AnyValidBuilder = Union[MSim,XVHDL, GHDL]
AnyValidBuilder = Union[MSim,XSIM, GHDL]
AnyBuilder = Union[AnyValidBuilder, Fallback]


Expand All@@ -66,7 +66,7 @@ class BuilderName(Enum):
"""

msim = MSim.builder_name
xvhdl =XVHDL.builder_name
xsim =XSIM.builder_name
ghdl = GHDL.builder_name
fallback = Fallback.builder_name

Expand All@@ -77,8 +77,8 @@ def getBuilderByName(name):
# builder attribute
if name == "msim":
builder = MSim
elif name == "xvhdl":
builder =XVHDL
elif name == "xsim":
builder =XSIM
elif name == "ghdl":
builder = GHDL
else:
Expand DownExpand Up@@ -201,7 +201,7 @@ def _getSourcesFromVUnitModule(vunit_module):
return list(vunit_project.get_source_files())


__all__ = ["MSim", "XVHDL", "GHDL", "Fallback"]
__all__ = ["MSim", "XSIM", "GHDL", "Fallback"]

# This holds the builders in order of preference
AVAILABLE_BUILDERS = MSim,XVHDL, GHDL, Fallback
AVAILABLE_BUILDERS = MSim,XSIM, GHDL, Fallback
20 changes: 10 additions & 10 deletionshdl_checker/builders/xvhdl.py → hdl_checker/builders/xsim.py
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Expand Up@@ -14,7 +14,7 @@
#
# You should have received a copy of the GNU General Public License
# along with HDL Checker. If not, see <http://www.gnu.org/licenses/>.
"Xilinxxhvdl builder implementation"
"XilinxSimulator builder implementation"

import os.path as p
import re
Expand All@@ -37,7 +37,7 @@
flags=re.I,
).finditer

#XVHDL specific class properties
#XSIM specific class properties
_STDOUT_MESSAGE_SCANNER = re.compile(
r"^(?P<severity>[EW])\w+:\s*"
r"\[(?P<error_code>[^\]]+)\]\s*"
Expand All@@ -50,11 +50,11 @@
)


classXVHDL(BaseBuilder):
classXSIM(BaseBuilder):
"""Builder implementation of the xvhdl compiler"""

# Implementation of abstract class properties
builder_name = "xvhdl"
builder_name = "xsim"
# TODO: Add xvlog support
file_types = {FileType.vhdl}

Expand All@@ -75,10 +75,10 @@ def _shouldIgnoreLine(self, line):
def __init__(self, *args, **kwargs):
# type: (...) -> None
self._version = ""
super(XVHDL, self).__init__(*args, **kwargs)
self._xvhdlini = p.join(self._work_folder, ".xvhdl.init")
super(XSIM, self).__init__(*args, **kwargs)
self._xsimini = p.join(self._work_folder, ".xsim.init")
# Create the ini file
open(self._xvhdlini, "w").close()
open(self._xsimini, "w").close()

def _makeRecords(self, line):
# type: (str) -> Iterable[BuilderDiag]
Expand All@@ -105,7 +105,7 @@ def _makeRecords(self, line):
)

def _parseBuiltinLibraries(self):
"(Not used byXVHDL)"
"(Not used byXSIM)"
return (
Identifier(x, case_sensitive=False)
for x in (
Expand DownExpand Up@@ -144,7 +144,7 @@ def isAvailable():

def _createLibrary(self, library):
# type: (Identifier) -> None
with open(self._xvhdlini, mode="w") as fd:
with open(self._xsimini, mode="w") as fd:
content = "\n".join(
[
"%s=%s" % (x, p.join(self._work_folder, x.name))
Expand All@@ -161,7 +161,7 @@ def _buildSource(self, path, library, flags=None):
"--verbose",
"0",
"--initfile",
self._xvhdlini,
self._xsimini,
"--work",
library.name,
]
Expand Down
4 changes: 2 additions & 2 deletionshdl_checker/serialization.py
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Expand Up@@ -22,7 +22,7 @@
from hdl_checker.builders.fallback import Fallback
from hdl_checker.builders.ghdl import GHDL
from hdl_checker.builders.msim import MSim
from hdl_checker.builders.xvhdl importXVHDL
from hdl_checker.builders.xsim importXSIM
from hdl_checker.database import Database
from hdl_checker.parsers.elements.dependency_spec import (
IncludedPath,
Expand DownExpand Up@@ -60,7 +60,7 @@
"VerilogDesignUnit": VerilogDesignUnit,
"VhdlIdentifier": VhdlIdentifier,
"VhdlParser": VhdlParser,
"XVHDL":XVHDL,
"XSIM":XSIM,
}


Expand Down
8 changes: 4 additions & 4 deletionshdl_checker/tests/__init__.py
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Expand Up@@ -266,7 +266,7 @@ def getBuilderByName(name):
"Returns the builder class given a string name"
from hdl_checker.builders.msim import MSim
from hdl_checker.builders.ghdl import GHDL
from hdl_checker.builders.xvhdl importXVHDL
from hdl_checker.builders.xsim importXSIM
from hdl_checker.builders.fallback import Fallback

# Check if the builder selected is implemented and create the
Expand All@@ -276,8 +276,8 @@ def getBuilderByName(name):
return MockBuilder
if name == "msim":
return MSim
if name == "xvhdl":
returnXVHDL
if name == "xsim":
returnXSIM
if name == "ghdl":
return GHDL

Expand DownExpand Up@@ -391,7 +391,7 @@ def writeListToFile(filename, _list): # pragma: no cover
TEST_ENVS = {
"ghdl": os.environ["GHDL_PATH"],
"msim": os.environ["MODELSIM_PATH"],
"xvhdl": os.environ["XSIM_PATH"],
"xsim": os.environ["XSIM_PATH"],
"fallback": None,
}
else:
Expand Down
6 changes: 3 additions & 3 deletionshdl_checker/tests/test_builder_utils.py
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Expand Up@@ -37,7 +37,7 @@
from hdl_checker.builders.fallback import Fallback
from hdl_checker.builders.ghdl import GHDL
from hdl_checker.builders.msim import MSim
from hdl_checker.builders.xvhdl importXVHDL
from hdl_checker.builders.xsim importXSIM
from hdl_checker.path import Path
from hdl_checker.types import FileType

Expand All@@ -55,7 +55,7 @@ def _path(*args):
class TestBuilderUtils(TestCase):
def test_getBuilderByName(self):
self.assertEqual(getBuilderByName("msim"), MSim)
self.assertEqual(getBuilderByName("xvhdl"),XVHDL)
self.assertEqual(getBuilderByName("xsim"),XSIM)
self.assertEqual(getBuilderByName("ghdl"), GHDL)
self.assertEqual(getBuilderByName("other"), Fallback)

Expand DownExpand Up@@ -214,7 +214,7 @@ def test_VhdlAndSystemverilogOnlyBuilder(
]

builder = MagicMock()
builder.builder_name = "xvhdl"
builder.builder_name = "xsim"
builder.file_types = {FileType.vhdl, FileType.systemverilog}

self.assertTrue(foundVunit(), "Need VUnit for this test")
Expand Down
20 changes: 10 additions & 10 deletionshdl_checker/tests/test_builders.py
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Original file line numberDiff line numberDiff line change
Expand Up@@ -42,7 +42,7 @@
from hdl_checker.builder_utils import (
AVAILABLE_BUILDERS,
GHDL,
XVHDL,
XSIM,
AnyBuilder,
Fallback,
MSim,
Expand DownExpand Up@@ -71,7 +71,7 @@
TEST_TEMP_PATH = getTestTempPath(__name__)
SOURCES_PATH = p.join(TEST_TEMP_PATH, "test_builders")

BUILDER_CLASS_MAP = {"msim": MSim, "xvhdl":XVHDL, "ghdl": GHDL, "fallback": Fallback}
BUILDER_CLASS_MAP = {"msim": MSim, "xsim":XSIM, "ghdl": GHDL, "fallback": Fallback}


class _SourceMock(SourceMock):
Expand DownExpand Up@@ -369,10 +369,10 @@ def test_ParseGhdlResult(self, path):
("some_file_on_same_level.vhd",),
]
)
deftest_ParseXvhdlResult(self, path):
deftest_ParseXsimResult(self, path):
# type: (...) -> Any
if not isinstance(self.builder,XVHDL):
raise unittest2.SkipTest("XVHDL only test")
if not isinstance(self.builder,XSIM):
raise unittest2.SkipTest("XSIM only test")

self.assertEqual(
list(
Expand DownExpand Up@@ -517,8 +517,8 @@ def test_CatchAKnownError(self):
),
}
]
elif self.builder_name == "xvhdl":
#XVHDL reports different errors depending on the version
elif self.builder_name == "xsim":
#XSIM reports different errors depending on the version
expected = [
{
BuilderDiag(
Expand DownExpand Up@@ -603,10 +603,10 @@ def test_GhdlRecompileMsg(self):
list(self.builder._searchForRebuilds(Path("foo.vhd"), line)),
)

deftest_XvhdlRecompileMsg0(self):
deftest_XsimRecompileMsg0(self):
# type: (...) -> Any
if not isinstance(self.builder,XVHDL):
raise unittest2.SkipTest("XVHDL only test")
if not isinstance(self.builder,XSIM):
raise unittest2.SkipTest("XSIM only test")

line = (
"ERROR: [VRFC 10-113] {} needs to be re-saved since std.standard "
Expand Down
4 changes: 2 additions & 2 deletionshdl_checker/tests/test_misc.py
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Expand Up@@ -36,7 +36,7 @@
from hdl_checker.builders.fallback import Fallback
from hdl_checker.builders.ghdl import GHDL
from hdl_checker.builders.msim import MSim
from hdl_checker.builders.xvhdl importXVHDL
from hdl_checker.builders.xsim importXSIM
from hdl_checker.utils import _getLatestReleaseVersion, onNewReleaseFound, readFile

_logger = logging.getLogger(__name__)
Expand DownExpand Up@@ -97,7 +97,7 @@ class TestBuilderUtils(unittest2.TestCase):
def test_getBuilderByName(self):
self.assertEqual(getBuilderByName(BuilderName.msim.value), MSim)
self.assertEqual(getBuilderByName(BuilderName.ghdl.value), GHDL)
self.assertEqual(getBuilderByName(BuilderName.xvhdl.value),XVHDL)
self.assertEqual(getBuilderByName(BuilderName.xsim.value),XSIM)
self.assertEqual(getBuilderByName("foo"), Fallback)


Expand Down
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