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Commitdb9c0a2

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Activate default clocks on the stm32wb with semaphore
This procedure is preventing the M0 to access the RCCduring the clock enabled by the M4.Signed-off-by: Francois Ramu <francois.ramu@st.com>
1 parent60d2609 commitdb9c0a2

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2 files changed

+34
-4
lines changed

2 files changed

+34
-4
lines changed

‎src/utility/HCISharedMemTransport.cpp

Lines changed: 31 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -555,11 +555,38 @@ void HCISharedMemTransportClass::start_ble_rf(void)
555555
{
556556
if ((LL_RCC_IsActiveFlag_PINRST()) && (!LL_RCC_IsActiveFlag_SFTRST())) {
557557
/* Simulate power off reset*/
558-
LL_PWR_EnableBkUpAccess();
559-
LL_PWR_EnableBkUpAccess();
560-
LL_RCC_ForceBackupDomainReset();
561-
LL_RCC_ReleaseBackupDomainReset();
558+
562559
}
560+
561+
/* HW semaphore Clock is enabled for this variant*/
562+
LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
563+
564+
//* This prevents the CPU2 (M0+) to configure RCC */
565+
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
566+
567+
#ifdef LL_APB1_GRP1_PERIPH_PWR
568+
/* Enable the power interface clock*/
569+
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
570+
#endif
571+
/* Set the DBP bit in the Power control register 1 (PWR_CR1)*/
572+
LL_PWR_EnableBkUpAccess();
573+
574+
/* LSE belongs to the back-up domain, enable access.*/
575+
while (!LL_PWR_IsEnabledBkUpAccess()) {
576+
/* Wait for Backup domain access*/
577+
}
578+
LL_RCC_ForceBackupDomainReset();
579+
LL_RCC_ReleaseBackupDomainReset();
580+
581+
/* Enable LSE Oscillator (32.768 kHz)*/
582+
LL_RCC_LSE_Enable();
583+
while (!LL_RCC_LSE_IsReady()) {
584+
/* Wait for LSE ready*/
585+
}
586+
587+
LL_PWR_DisableBkUpAccess();
588+
589+
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID,0);
563590

564591
/* Switch OFF LSI as LSE is the source clock*/
565592
LL_RCC_LSI2_Disable();

‎src/utility/HCISharedMemTransport.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@
2525
/* STM32WB include files*/
2626
#include"stm32wb55xx.h"
2727
#include"stm32wbxx_ll_rcc.h"
28+
#include"stm32wbxx_ll_hsem.h"
2829
#include"stm32wbxx_ll_ipcc.h"
2930
#include"stm32wbxx_ll_system.h"
3031
#include"STM32Cube_FW/tl.h"
@@ -38,6 +39,8 @@
3839
/* this CONFIG_DEBUG must be defined for -Og option*/
3940
//#define CONFIG_DEBUG
4041

42+
#defineCFG_HW_RCC_SEMID3U
43+
4144
/******************************************************************************
4245
* BLE config parameters
4346
******************************************************************************/

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