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chore(f7): update to latest STM32CubeF7 v1.17.3#2741

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Merged
fpistm merged 3 commits intostm32duino:mainfromfpistm:stm32cubef7_update
May 27, 2025
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Expand Up@@ -12824,7 +12824,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -12846,7 +12846,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -13069,7 +13069,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -13047,7 +13047,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -13069,7 +13069,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -13926,7 +13926,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -14274,7 +14274,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -14567,7 +14567,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -14567,7 +14567,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -14508,7 +14508,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -14902,7 +14902,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -14997,7 +14997,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -15195,7 +15195,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -15290,7 +15290,7 @@ typedef struct

/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
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Expand Up@@ -96,11 +96,11 @@
#endif /* USE_HAL_DRIVER */

/**
* @brief CMSIS Device version number V1.2.9
* @brief CMSIS Device version number V1.2.10
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x09) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x0A) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
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11 changes: 10 additions & 1 deletionsystem/Drivers/CMSIS/Device/ST/STM32F7xx/Release_Notes.html
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Expand Up@@ -30,7 +30,16 @@ <h1 id="release-notes-for-stm32f7xx-cmsis"><strong>Release Notes for STM32F7xx C
<div class="col-sm-12 col-lg-8">
<h1 id="update-history"><strong>Update History</strong></h1>
<div class="collapse">
<input type="checkbox" id="collapse-section1_2_9" checked aria-hidden="true"> <label for="collapse-section1_2_9" aria-hidden="true"><strong>V1.2.9 / 10-May-2024</strong></label>
<input type="checkbox" id="collapse-section1_2_10" checked aria-hidden="true"> <label for="collapse-section1_2_10" aria-hidden="true"><strong>V1.2.10 / 25-April-2025</strong></label>
<div>
<ul>
<li>Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.</li>
<li>Fix Capture Compare register TIMx_CCR5 defintion.</li>
</ul>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section1_2_9" aria-hidden="true"> <label for="collapse-section1_2_9" aria-hidden="true"><strong>V1.2.9 / 10-May-2024</strong></label>
<div>
<ul>
<li>Update GCC start-up files to call SystemInit() API <span class="citation" data-cites="Reset_Handler">@Reset_Handler</span> step: alignment with EWARM and MDK-ARM start-up files.</li>
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Expand Up@@ -86,14 +86,14 @@
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#if !defined(VECT_TAB_OFFSET)
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_OFFSET */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/

Expand DownExpand Up@@ -199,7 +199,7 @@ void SystemInit(void)
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
uint32_t tmp, pllvco, pllp, pllsource, pllm;

/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
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Expand Up@@ -6,7 +6,7 @@
* STM32F2: 2.2.6
* STM32F3: 2.3.8
* STM32F4: 2.6.10
* STM32F7: 1.2.9
* STM32F7: 1.2.10
* STM32G0: 1.4.4
* STM32G4: 1.2.5
* STM32H5: 1.4.0
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