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Optimize H573RI/H503KB/H503RB clock config.#2507
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fpistm requested changesSep 2, 2024
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eb4da94 to9e8b242CompareComplement ofstm32duino#2506Signed-off-by: Kazuki Ota <ota_droid@live.jp>Co-Authored-by: Frederic Pillon <frederic.pillon@st.com>
9e8b242 to1f17775Comparefpistm approved these changesSep 3, 2024
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Basically same as "Optimize PLL ratio" in#2506.
Summary
This PR fixes/implements the followingbugs/features
By setting
SRC / M = 2N = 250for PLL1/2/3 you can flexibly determine clock source frequency and easily calculate division P/Q/R.CubeMX Screenshots
for H503KB/H503RB

for H573RI
