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Fix H563ZI clock config.#2506

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fpistm merged 1 commit intostm32duino:mainfromdojyorin:fix-h563zi-clock
Sep 3, 2024
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@dojyorindojyorin commentedAug 29, 2024•
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Summary

This PR fixes/implements the followingbugs/features

  • ADC/DAC input clock is too high
  • LPUART clock is low
  • Optimize PLL ratio
  • There were no plans to change LPUART, but since it will be lower than current value when I fix ADC/DAC problem, I changed it as described inIncorrect clock settings for NUCLEO-H563ZI #2505.
  • By settingSRC / M = 2N = 250 for PLL1/2/3 you can flexibly determine clock source frequency and easily calculate division P/Q/R.

e.g. Generic boards and NUCLEO-H563ZI are portable by simply changing value of PLLM.

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  • for H563ZI
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  • Demonstrate the code is solid. [e.g. Provide a sketch]

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Closing issues

Fixes#2505

@dojyorindojyorin changed the titleFix H563ZI clock config. (#3)Fix H563ZI clock config.Aug 29, 2024
@fpistmfpistm self-requested a reviewSeptember 2, 2024 08:44
@fpistmfpistm added the enhancementNew feature or request labelSep 2, 2024
@fpistmfpistm added this to the2.9.0 milestoneSep 2, 2024
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Clock config is not correct.

Remove all HSI usage.Fix ADC/DAC clock frequency (125MHz).Signed-off-by: Kazuki Ota <ota_droid@live.jp>Co-Authored-by: Frederic Pillon <frederic.pillon@st.com>
@fpistmfpistm merged commit56655f3 intostm32duino:mainSep 3, 2024
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fpistm added a commit to dojyorin/Arduino_Core_STM32 that referenced this pull requestSep 3, 2024
Complement ofstm32duino#2506Signed-off-by: Kazuki Ota <ota_droid@live.jp>Co-Authored-by: Frederic Pillon <frederic.pillon@st.com>
fpistm added a commit that referenced this pull requestSep 3, 2024
Complement of#2506Signed-off-by: Kazuki Ota <ota_droid@live.jp>Co-Authored-by: Frederic Pillon <frederic.pillon@st.com>
@dojyorindojyorin deleted the fix-h563zi-clock branchMarch 19, 2025 14:38
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Incorrect clock settings for NUCLEO-H563ZI
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