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Update to latest STM32CubeL1 v1.10.4#2014

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Merged
fpistm merged 4 commits intostm32duino:mainfromfpistm:CubeL1_v1.10.4
Jun 1, 2023
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2 changes: 2 additions & 0 deletionslibraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c
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Original file line numberDiff line numberDiff line change
Expand Up@@ -20,6 +20,8 @@
#include "stm32h7xx_hal_smbus.c"
#elif STM32L0xx
#include "stm32l0xx_hal_smbus.c"
#elif STM32L1xx
#include "stm32l1xx_hal_smbus.c"
#elif STM32L4xx
#include "stm32l4xx_hal_smbus.c"
#elif STM32L5xx
Expand Down
47 changes: 27 additions & 20 deletionssystem/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h
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Original file line numberDiff line numberDiff line change
Expand Up@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral�s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
*<h2><center>&copy;Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
Expand DownExpand Up@@ -863,7 +862,7 @@ typedef struct
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC dataalignement */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC dataalignment */

#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
Expand DownExpand Up@@ -2751,7 +2750,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L1serie)
* @brief Specific device feature definitions (not present on all devices in the STM32L1series)
*/
#define FLASH_CUT1

Expand DownExpand Up@@ -3658,7 +3657,7 @@ typedef struct

#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
Expand DownExpand Up@@ -4465,7 +4464,7 @@ typedef struct
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */

/*!< RTCcongiguration */
/*!< RTCconfiguration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
Expand DownExpand Up@@ -4515,7 +4514,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
Expand DownExpand Up@@ -5006,7 +5005,7 @@ typedef struct
/******************************************************************************/

/*
* @brief Specific device feature definitions (not present on all devices in the STM32F3serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F3series)
*/

/******************* Bit definition for SPI_CR1 register ********************/
Expand DownExpand Up@@ -6078,12 +6077,21 @@ typedef struct
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */

/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_DIV_FRACTION_Pos (0U)
#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
#define USART_BRR_DIV_MANTISSA_Pos (4U)
#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
#define USART_BRR_DIV_Fraction_Pos (0U)
#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
#define USART_BRR_DIV_Mantissa_Pos (4U)
#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */

/* Legacy aliases */
#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction

#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa

/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
Expand DownExpand Up@@ -7666,4 +7674,3 @@ typedef struct



/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
49 changes: 28 additions & 21 deletionssystem/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h
View file
Open in desktop
Original file line numberDiff line numberDiff line change
Expand Up@@ -9,18 +9,17 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral�s registers hardware
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
*<h2><center>&copy;Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2017-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
Expand DownExpand Up@@ -863,7 +862,7 @@ typedef struct
#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
#define ADC_CR2_ALIGN_Pos (11U)
#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC dataalignement */
#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC dataalignment */

#define ADC_CR2_JEXTSEL_Pos (16U)
#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
Expand DownExpand Up@@ -2754,7 +2753,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32L1serie)
* @brief Specific device feature definitions (not present on all devices in the STM32L1series)
*/
#define FLASH_CUT2

Expand DownExpand Up@@ -3664,7 +3663,7 @@ typedef struct

#define LCD_FCR_PON_Pos (4U)
#define LCD_FCR_PON_Msk (0x7UL << LCD_FCR_PON_Pos) /*!< 0x00000070 */
#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
#define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Pulse ON Duration) */
#define LCD_FCR_PON_0 (0x1UL << LCD_FCR_PON_Pos) /*!< 0x00000010 */
#define LCD_FCR_PON_1 (0x2UL << LCD_FCR_PON_Pos) /*!< 0x00000020 */
#define LCD_FCR_PON_2 (0x4UL << LCD_FCR_PON_Pos) /*!< 0x00000040 */
Expand DownExpand Up@@ -3833,7 +3832,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0series)
*/
#define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */

Expand DownExpand Up@@ -4492,7 +4491,7 @@ typedef struct
#define RCC_CSR_RTCSEL_0 (0x1UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
#define RCC_CSR_RTCSEL_1 (0x2UL << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */

/*!< RTCcongiguration */
/*!< RTCconfiguration */
#define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
#define RCC_CSR_RTCSEL_LSE_Pos (16U)
#define RCC_CSR_RTCSEL_LSE_Msk (0x1UL << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
Expand DownExpand Up@@ -4542,7 +4541,7 @@ typedef struct
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32F0serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F0series)
*/
#define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
#define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
Expand DownExpand Up@@ -5154,7 +5153,7 @@ typedef struct
/******************************************************************************/

/*
* @brief Specific device feature definitions (not present on all devices in the STM32F3serie)
* @brief Specific device feature definitions (not present on all devices in the STM32F3series)
*/

/******************* Bit definition for SPI_CR1 register ********************/
Expand DownExpand Up@@ -6226,12 +6225,21 @@ typedef struct
#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */

/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_DIV_FRACTION_Pos (0U)
#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
#define USART_BRR_DIV_MANTISSA_Pos (4U)
#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
#define USART_BRR_DIV_Fraction_Pos (0U)
#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
#define USART_BRR_DIV_Mantissa_Pos (4U)
#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */

/* Legacy aliases */
#define USART_BRR_DIV_FRACTION_Pos USART_BRR_DIV_Fraction_Pos
#define USART_BRR_DIV_FRACTION_Msk USART_BRR_DIV_Fraction_Msk
#define USART_BRR_DIV_FRACTION USART_BRR_DIV_Fraction

#define USART_BRR_DIV_MANTISSA_Pos USART_BRR_DIV_Mantissa_Pos
#define USART_BRR_DIV_MANTISSA_Msk USART_BRR_DIV_Mantissa_Msk
#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_Mantissa

/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_SBK_Pos (0U)
Expand DownExpand Up@@ -7814,4 +7822,3 @@ typedef struct



/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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