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Added support for STM32F412Zx MCU#2011

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Merged
fpistm merged 2 commits intostm32duino:mainfromToritos01:main
May 16, 2023
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2 changes: 2 additions & 0 deletionsREADME.md
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Original file line numberDiff line numberDiff line change
Expand Up@@ -87,6 +87,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| Status | Device(s) | Name | Release | Notes |
| :----: | :-------: | ---- | :-----: | :---- |
| :green_heart: | STM32F207ZG | [Nucleo F207ZG](http://www.st.com/en/evaluation-tools/nucleo-f207zg.html) | *0.2.0* | |
| :yellow_heart: | STM32F412ZG | [Nucleo F412ZG](http://www.st.com/en/evaluation-tools/nucleo-f412zg.html) | **2.6.0** | |
| :green_heart: | STM32F429ZI | [Nucleo F429ZI](http://www.st.com/en/evaluation-tools/nucleo-f429zi.html) | *0.1.0* | |
| :green_heart: | STM32F722ZE | [Nucleo F722ZE](http://www.st.com/en/evaluation-tools/nucleo-f722ze.html) | *2.4.0* | |
| :green_heart: | STM32F767ZI | [Nucleo F767ZI](http://www.st.com/en/evaluation-tools/nucleo-f767zi.html) | *1.4.0* | |
Expand DownExpand Up@@ -344,6 +345,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32F411RC<br>STM32F411RE | Generic Board | *1.9.0* | |
| :green_heart: | STM32F412CE<br>STM32F412CG | Generic Board | *1.9.0* | |
| :green_heart: | STM32F412RE<br>STM32F412RG | Generic Board | *1.9.0* | |
| :yellow_heart: | STM32F412ZE<br>STM32F412ZG | Generic Board | **2.6.0** | |
| :green_heart: | STM32F413CG<br>STM32F413CH | Generic Board | *1.9.0* | |
| :green_heart: | STM32F413RG<br>STM32F413RH | Generic Board | *1.9.0* | |
| :green_heart: | STM32F413ZG<br>STM32F413ZH | Generic Board | *2.0.0* | |
Expand Down
46 changes: 46 additions & 0 deletionsboards.txt
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Expand Up@@ -37,6 +37,20 @@ Nucleo_144.menu.pnum.NUCLEO_F207ZG.build.variant=STM32F2xx/F207Z(C-E-F-G)T_F217Z
Nucleo_144.menu.pnum.NUCLEO_F207ZG.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS
Nucleo_144.menu.pnum.NUCLEO_F207ZG.build.cmsis_lib_gcc=arm_cortexM3l_math

# NUCLEO_F412ZG board
Nucleo_144.menu.pnum.NUCLEO_F412ZG=Nucleo F412ZG
Nucleo_144.menu.pnum.NUCLEO_F412ZG.node=NODE_F412ZG
Nucleo_144.menu.pnum.NUCLEO_F412ZG.upload.maximum_size=1048576
Nucleo_144.menu.pnum.NUCLEO_F412ZG.upload.maximum_data_size=262144
Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.mcu=cortex-m4
Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.fpu=-mfpu=fpv4-sp-d16
Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.float-abi=-mfloat-abi=hard
Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.board=NUCLEO_F412ZG
Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.series=STM32F4xx
Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.product_line=STM32F412Zx
Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.variant=STM32F4xx/F412Z(E-G)(J-T)
Nucleo_144.menu.pnum.NUCLEO_F412ZG.build.cmsis_lib_gcc=arm_cortexM4lf_math

# NUCLEO_F413ZH board
Nucleo_144.menu.pnum.NUCLEO_F413ZH=Nucleo F413ZH
Nucleo_144.menu.pnum.NUCLEO_F413ZH.node=NODE_F413ZH
Expand DownExpand Up@@ -4113,6 +4127,38 @@ GenF4.menu.pnum.GENERIC_F412RGYXP.build.board=GENERIC_F412RGYXP
GenF4.menu.pnum.GENERIC_F412RGYXP.build.product_line=STM32F412Rx
GenF4.menu.pnum.GENERIC_F412RGYXP.build.variant=STM32F4xx/F412R(E-G)(T-Y)x(P)

# Generic F412ZEJx
GenF4.menu.pnum.GENERIC_F412ZEJX=Generic F412ZEJx
GenF4.menu.pnum.GENERIC_F412ZEJX.upload.maximum_size=524288
GenF4.menu.pnum.GENERIC_F412ZEJX.upload.maximum_data_size=262144
GenF4.menu.pnum.GENERIC_F412ZEJX.build.board=GENERIC_F412ZEJX
GenF4.menu.pnum.GENERIC_F412ZEJX.build.product_line=STM32F412Zx
GenF4.menu.pnum.GENERIC_F412ZEJX.build.variant=STM32F4xx/F412Z(E-G)(J-T)

# Generic F412ZGJx
GenF4.menu.pnum.GENERIC_F412ZGJX=Generic F412ZGJx
GenF4.menu.pnum.GENERIC_F412ZGJX.upload.maximum_size=1048576
GenF4.menu.pnum.GENERIC_F412ZGJX.upload.maximum_data_size=262144
GenF4.menu.pnum.GENERIC_F412ZGJX.build.board=GENERIC_F412ZGJX
GenF4.menu.pnum.GENERIC_F412ZGJX.build.product_line=STM32F412Zx
GenF4.menu.pnum.GENERIC_F412ZGJX.build.variant=STM32F4xx/F412Z(E-G)(J-T)

# Generic F412ZETx
GenF4.menu.pnum.GENERIC_F412ZETX=Generic F412ZETx
GenF4.menu.pnum.GENERIC_F412ZETX.upload.maximum_size=524288
GenF4.menu.pnum.GENERIC_F412ZETX.upload.maximum_data_size=262144
GenF4.menu.pnum.GENERIC_F412ZETX.build.board=GENERIC_F412ZETX
GenF4.menu.pnum.GENERIC_F412ZETX.build.product_line=STM32F412Zx
GenF4.menu.pnum.GENERIC_F412ZETX.build.variant=STM32F4xx/F412Z(E-G)(J-T)

# Generic F412ZGTx
GenF4.menu.pnum.GENERIC_F412ZGTX=Generic F412ZGTx
GenF4.menu.pnum.GENERIC_F412ZGTX.upload.maximum_size=1048576
GenF4.menu.pnum.GENERIC_F412ZGTX.upload.maximum_data_size=262144
GenF4.menu.pnum.GENERIC_F412ZGTX.build.board=GENERIC_F412ZGTX
GenF4.menu.pnum.GENERIC_F412ZGTX.build.product_line=STM32F412Zx
GenF4.menu.pnum.GENERIC_F412ZGTX.build.variant=STM32F4xx/F412Z(E-G)(J-T)

# Generic F413CGUx
GenF4.menu.pnum.GENERIC_F413CGUX=Generic F413CGUx
GenF4.menu.pnum.GENERIC_F413CGUX.upload.maximum_size=1048576
Expand Down
49 changes: 47 additions & 2 deletionsvariants/STM32F4xx/F412Z(E-G)(J-T)/generic_clock.c
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Expand Up@@ -21,8 +21,53 @@
*/
WEAK void SystemClock_Config(void)
{
/* SystemClock_Config can be generated by STM32CubeMX */
#warning "SystemClock_Config() is empty. Default clock at reset is used."
RCC_OscInitTypeDef RCC_OscInitStruct = {};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};

/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);

/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 96;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLR = 2;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Error_Handler();
}

/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
Error_Handler();
}

/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_CLK48;
PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLQ;
PeriphClkInitStruct.SdioClockSelection = RCC_SDIOCLKSOURCE_CLK48;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
Error_Handler();
}
}

#endif /* ARDUINO_GENERIC_* */
185 changes: 185 additions & 0 deletionsvariants/STM32F4xx/F412Z(E-G)(J-T)/ldscript.ld
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@@ -0,0 +1,185 @@
/*
******************************************************************************
**
** @file : LinkerScript.ld
**
** @author : Auto-generated by STM32CubeIDE
**
** @brief : Linker script for STM32F412ZGTx Device from STM32F4 series
** 1024Kbytes FLASH
** 256Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed as is, without any warranty
** of any kind.
**
******************************************************************************
** @attention
**
** Copyright (c) 2023 STMicroelectronics.
** All rights reserved.
**
** This software is licensed under terms that can be found in the LICENSE file
** in the root directory of this software component.
** If no LICENSE file comes with this software, it is provided AS-IS.
**
******************************************************************************
*/

/* Entry Point */
ENTRY(Reset_Handler)

/* Highest address of the user mode stack */
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */

_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */

/* Memories definition */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
}

/* Sections */
SECTIONS
{
/* The startup code into "FLASH" Rom type memory */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH

/* The program code and other data into "FLASH" Rom type memory */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)

KEEP (*(.init))
KEEP (*(.fini))

. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH

/* Constant data into "FLASH" Rom type memory */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH

.ARM.extab : {
. = ALIGN(4);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(4);
} >FLASH

.ARM : {
. = ALIGN(4);
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
. = ALIGN(4);
} >FLASH

.preinit_array :
{
. = ALIGN(4);
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH

.init_array :
{
. = ALIGN(4);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH

.fini_array :
{
. = ALIGN(4);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} >FLASH

/* Used by the startup to initialize data */
_sidata = LOADADDR(.data);

/* Initialized data sections into "RAM" Ram type memory */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
*(.RamFunc) /* .RamFunc sections */
*(.RamFunc*) /* .RamFunc* sections */

. = ALIGN(4);
_edata = .; /* define a global symbol at data end */

} >RAM AT> FLASH

/* Uninitialized data section into "RAM" Ram type memory */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)

. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM

/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM

/* Remove information from the compiler libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}

.ARM.attributes 0 : { *(.ARM.attributes) }
}
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