Hello,
I know that parts of this issue have been already discussed and I am sorry for repeating some. Unfortunately I couldn't find a working solution for my problem. Hopefully anybody can help. Hardwares-setup: I am using an STM32 F446RE board. Vbat is supplied by 3V battery.

LSI CLOCK
(no clocktype setup, or use of commandRTC.setClockSource(STM32RTC::LSI_CLOCK);):

• the RTCworks, as long the board is powered
• accuracy is tolerable but not perfect (~2 seconds of deviation after a few minutes)
• RTC clock source selection in RCC_BDCR is set10: LSI oscillator clock used as the RTC clock (seems good)
• when board is not powered for 5 minutes and then powered again:
  • the RTC continues with the last time, before being switched off (the 5 minutes never existed)
  • RTC.isTimeSet() returnstrueat startup
  • so backup domain works generally and is kept on power by battery, BUT the RTC is no continuing to count the time.

LSE CLOCK
(byRTC.setClockSource(STM32RTC::LSE_CLOCK);)

• the RTC works, as long as the board is powered
• accuracy seems to be quiet good
• RTC clock source selection in RCC_BDCR is set01: LSE oscillator clock used as the RTC clock (seems good)
• once the board is powered off and on again,
  • all RTC information are lost
  • RTC.isTimeSet() returnsfalse at startup
  • backup domain seems not to be working at all (at least at startup I can prove that)

HSE CLOCK
(byRTC.setClockSource(STM32RTC::HSE_CLOCK);)

• not working, since no HSE oscillator -> CPU stucks when power on

I want to use the LSE clock, but it doesn't keep anything in the backupdomain, whereas LSI does, but not counting time.
Does anybody has an idea what is wrong, and how I can realize a working setup?

Thank you in advance!

Additionally here are a few, maybe relevant register entries:

RCC_CR(clock control register):HSION - 1: HSI oscillator ONHSIRDY - 1: HSI oscillator readyHSITRIM - 0x10HSICAL - 0x73HSEON - 0: HSE oscillator OFFHSERDY - 0: HSE oscillator not readyHSEBYP - 0: HSE oscillator not bypassedCSSON - 0: Clock security system OFF (Clock detector OFF)

RCC_PLLCFGR(PLL configuration register):PLLM - 001000: PLLM = 8PLLN - 010110100: PLLN = 180 PLLP - 00: PLLP = 2PLLSRC - 0: HSI clock selected as PLL and PLLI2S clock entryPLLQ - 0010: PLLQ = 2

RCC_CFGR(clock configuration register):SW - 10: PLL_P selected as system clockSWS - 10: PLL used as the system clockHPRE - 0: system clock not dividedPPRE1 - 101: AHB clock divided by 4PPRE2 - 100: AHB clock divided by 2RTCPRE - 00000: no clockMCO - 00: HSI clock selectedMCO1PRE - 0: no divisionMCO2PRE - 0: no divisionMCO2 - 00: System clock (SYSCLK) selected

RCC_BDCR(Backup domain control register):LSEON - 1: LSE clock ONLSERDY - 1: LSE clock readyLSEBYP - 0: LSE oscillator not bypassedLSEMOD - 0: LSE oscillator "low power" mode selectionRTCSEL - 10: LSI oscillator clock used as the RTC clockBDRST - 0: Reset not activated

RCC_CSR(clock control & status register):LSION - 1: LSI RC oscillator ONLSIRDY - 1: LSI RC oscillator ready[...]

RTC_PRER(RTC prescaler register):PREDIV_S - PREDIV_S = 249PREDIV_A - PREDIV_A = 127