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Commitf5ee1b4

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variants(h7): add Nucleo-H743ZG
Signed-off-by: yetanothercarbot <55005345+yetanothercarbot@users.noreply.github.com>Co-authored-by: Frederic Pillon <frederic.pillon@st.com>
1 parenta43419e commitf5ee1b4

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‎README.md

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@@ -96,6 +96,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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|:green_heart:| STM32L4R5ZI|[Nucleo L4R5ZI](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html)|*1.4.0*||
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|:green_heart:| STM32L4R5ZI-P|[Nucleo L4R5ZI-P](http://www.st.com/en/evaluation-tools/nucleo-l4r5zi-p.html)|*1.4.0*||
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|:green_heart:| STM32L552ZE-Q|[Nucleo L552ZE-Q](https://www.st.com/en/evaluation-tools/nucleo-l552ze-q.html)|*2.0.0*||
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|:yellow_heart:| STM32H723ZG|[Nucleo H723ZG](https://www.st.com/en/evaluation-tools/nucleo-h723zg.html)|**2.4.0**||
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|:green_heart:| STM32H743ZI|[Nucleo H743ZI(2)](https://www.st.com/en/evaluation-tools/nucleo-h743zi.html)|*1.5.0*| Nucleo H743ZI2 since 1.6.0|
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|:green_heart:| STM32U575ZI-Q|[NUCLEO-U575ZI-Q](https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html)|*2.1.0*||
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‎boards.txt

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@@ -123,6 +123,20 @@ Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.product_line=STM32F767xx
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Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.variant=STM32F7xx/F765Z(G-I)T_F767Z(G-I)T_F777ZIT
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Nucleo_144.menu.pnum.NUCLEO_F767ZI.build.cmsis_lib_gcc=arm_cortexM7lfsp_math
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# NUCLEO H723ZG board
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Nucleo_144.menu.pnum.NUCLEO_H723ZG=Nucleo H723ZG
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.node=NODE_H723ZG
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.upload.maximum_size=1048576
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.upload.maximum_data_size=327680
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.mcu=cortex-m7
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.fpu=-mfpu=fpv4-sp-d16
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.float-abi=-mfloat-abi=hard
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.board=NUCLEO_H723ZG
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.series=STM32H7xx
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.product_line=STM32H723xx
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.variant=STM32H7xx/H723Z(E-G)T_H730ZBT_H733ZGT
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Nucleo_144.menu.pnum.NUCLEO_H723ZG.build.cmsis_lib_gcc=arm_cortexM7lfsp_math
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# NUCLEO_H743ZI board
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Nucleo_144.menu.pnum.NUCLEO_H743ZI=Nucleo H743ZI
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Nucleo_144.menu.pnum.NUCLEO_H743ZI.node=NODE_H743ZI
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/*
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*******************************************************************************
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* Copyright (c) 2022, STMicroelectronics
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#if defined(ARDUINO_NUCLEO_H723ZG)
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#include"pins_arduino.h"
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// Pin number
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const PinName digitalPin[] = {
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PB_7,
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PB_6,
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PG_14,
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PE_13,
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PE_14,
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PE_11,
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PE_9,
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PG_12,
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PF_3,
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PD_15,
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PD_14,
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PB_5,
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PA_6,
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PA_5,
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PB_9,
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PB_8,
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PC_6,
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PB_15,
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PB_13,
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PB_12,
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PA_15,
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PC_7,
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PB_5,
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PB_3,
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PA_4,
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PB_4,
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PG_6,
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PB_2,
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PD_13,
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PD_12,
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PD_11,
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PE_2,
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PA_0,
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PB_0,
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PE_0,
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PB_11,
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PB_10,
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PE_15,
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PE_6,
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PE_12,
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PE_10,
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PE_7,
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PE_8,
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PC_8,
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PC_9,
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PC_10,
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PC_11,
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PC_12,
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PD_2,
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PG_2,
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PG_3,
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PD_7,
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PD_6,
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PD_5,
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PD_4,
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PD_3,
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PE_2,
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PE_4,
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PE_5,
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PE_6,
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PE_3,
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PF_8,
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PF_7,
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PF_9,
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PG_1,
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PG_0,
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PD_1,
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PD_0,
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PF_0,
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PF_1,
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PF_2,
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PE_9,
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PB_2,
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PA_3,
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PC_0,
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PC_3_C,
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PB_1,
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PC_2_C,
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PF_10,
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PF_4,
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PF_5,
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PF_6,
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PF_11,
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PA_1,
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PA_2,
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PA_7,
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PA_8,
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PA_9,
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PA_10,
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PA_11,
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PA_12,
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PA_13,
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PA_14,
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PB_14,
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PC_1,
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PC_4,
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PC_5,
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PC_13,
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PC_14,
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PC_15,
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PD_8,
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PD_9,
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PD_10,
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PE_1,
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PF_12,
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PF_13,
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PF_14,
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PF_15,
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PG_4,
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PG_5,
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PG_7,
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PG_8,
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PG_9,
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PG_10,
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PG_11,
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PG_13,
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PG_15,
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PH_0,
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PH_1
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};
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// Analog (Ax) pin number array
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constuint32_t analogInputPin[] = {
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73,// A0
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74,// A1
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75,// A2
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76,// A3
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77,// A4
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78,// A5
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79,// A6
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80,// A7
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81,// A8
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82,// A9
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83,// A10
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84,// A11
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85,// A12
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94,// A13
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95,// A14
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96,// A15
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104,// A16
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105,// A17
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106,// A18
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8,// A19
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12,// A20
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13,// A21
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24,// A22
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32,// A23
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33,// A24
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61,// A25
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62,// A26
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63// A27
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};
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// ----------------------------------------------------------------------------
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#ifdef __cplusplus
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extern"C" {
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#endif
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/**
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* @brief System Clock Configuration
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* @param None
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* @retval None
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*/
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WEAKvoidSystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
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/** Supply configuration update enable
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*/
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HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
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/** Configure the main internal regulator output voltage
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*/
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
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while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM =4;
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RCC_OscInitStruct.PLL.PLLN =275;
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RCC_OscInitStruct.PLL.PLLP =1;
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RCC_OscInitStruct.PLL.PLLQ =4;
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RCC_OscInitStruct.PLL.PLLR =2;
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RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
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RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
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RCC_OscInitStruct.PLL.PLLFRACN =0;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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Error_Handler();
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}
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
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| RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
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Error_Handler();
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}
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}
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#ifdef __cplusplus
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}
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#endif
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#endif/* ARDUINO_*/

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