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Commitf31d070

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Merge pull request#2353 from fpistm/STM32CubeWBA_update
chore(wba): update to latest STM32CubeWBA v1.3.1
2 parents0588a96 +a887b4d commitf31d070

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57 files changed

+953
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‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10295,6 +10295,10 @@ typedef struct
1029510295
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
1029610296
((INSTANCE) == TIM2_NS))
1029710297

10298+
/********* TIM Instances : supporting bitfield OCCS in SMCR register **********/
10299+
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
10300+
((INSTANCE) == TIM2_NS))
10301+
1029810302
/****************** TIM Instances : remapping capability **********************/
1029910303
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
1030010304
((INSTANCE) == TIM2_NS))

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h

Lines changed: 23 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -14343,8 +14343,7 @@ typedef struct
1434314343
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
1434414344

1434514345
/****************** TIM Instances : supporting 32 bits counter ****************/
14346-
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \
14347-
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
14346+
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S))
1434814347

1434914348
/****************** TIM Instances : supporting the break function *************/
1435014349
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
@@ -14530,6 +14529,11 @@ typedef struct
1453014529
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
1453114530
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
1453214531

14532+
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
14533+
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
14534+
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
14535+
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
14536+
1453314537
/****************** TIM Instances : remapping capability **********************/
1453414538
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
1453514539
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
@@ -14563,9 +14567,9 @@ typedef struct
1456314567
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S))
1456414568

1456514569
/****************** TIM Instances : supporting synchronization ****************/
14566-
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \
14567-
((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \
14568-
((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S))
14570+
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
14571+
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
14572+
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
1456914573

1457014574
/****************************** TSC Instances *********************************/
1457114575
#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S))
@@ -14791,8 +14795,7 @@ typedef struct
1479114795
((INSTANCE) == TIM17_NS))
1479214796

1479314797
/****************** TIM Instances : supporting 32 bits counter ****************/
14794-
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \
14795-
((INSTANCE) == TIM3_NS))
14798+
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS)
1479614799

1479714800
/****************** TIM Instances : supporting the break function *************/
1479814801
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
@@ -14974,9 +14977,16 @@ typedef struct
1497414977
((INSTANCE) == TIM3_NS))
1497514978

1497614979
/****************** TIM Instances : supporting OCxREF clear *******************/
14977-
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
14978-
((INSTANCE) == TIM2_NS) || \
14979-
((INSTANCE) == TIM3_NS))
14980+
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
14981+
((INSTANCE) == TIM2_NS) || \
14982+
((INSTANCE) == TIM3_NS) || \
14983+
((INSTANCE) == TIM16_NS) || \
14984+
((INSTANCE) == TIM17_NS))
14985+
14986+
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
14987+
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
14988+
((INSTANCE) == TIM2_NS) || \
14989+
((INSTANCE) == TIM3_NS))
1498014990

1498114991
/****************** TIM Instances : remapping capability **********************/
1498214992
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
@@ -15010,9 +15020,9 @@ typedef struct
1501015020
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS)
1501115021

1501215022
/****************** TIM Instances : supporting synchronization ****************/
15013-
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || \
15014-
((__INSTANCE__) == TIM2_NS) || \
15015-
((__INSTANCE__) == TIM3_NS))
15023+
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
15024+
((INSTANCE) == TIM2_NS) || \
15025+
((INSTANCE) == TIM3_NS))
1501615026

1501715027
/****************************** TSC Instances *********************************/
1501815028
#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS)

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h

Lines changed: 23 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -15051,8 +15051,7 @@ typedef struct
1505115051
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
1505215052

1505315053
/****************** TIM Instances : supporting 32 bits counter ****************/
15054-
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \
15055-
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
15054+
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S))
1505615055

1505715056
/****************** TIM Instances : supporting the break function *************/
1505815057
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
@@ -15238,6 +15237,11 @@ typedef struct
1523815237
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
1523915238
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
1524015239

15240+
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
15241+
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
15242+
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
15243+
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
15244+
1524115245
/****************** TIM Instances : remapping capability **********************/
1524215246
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
1524315247
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
@@ -15271,9 +15275,9 @@ typedef struct
1527115275
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S))
1527215276

1527315277
/****************** TIM Instances : supporting synchronization ****************/
15274-
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \
15275-
((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \
15276-
((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S))
15278+
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
15279+
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
15280+
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
1527715281

1527815282
/****************************** TSC Instances *********************************/
1527915283
#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S))
@@ -15499,8 +15503,7 @@ typedef struct
1549915503
((INSTANCE) == TIM17_NS))
1550015504

1550115505
/****************** TIM Instances : supporting 32 bits counter ****************/
15502-
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \
15503-
((INSTANCE) == TIM3_NS))
15506+
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS)
1550415507

1550515508
/****************** TIM Instances : supporting the break function *************/
1550615509
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
@@ -15682,9 +15685,16 @@ typedef struct
1568215685
((INSTANCE) == TIM3_NS))
1568315686

1568415687
/****************** TIM Instances : supporting OCxREF clear *******************/
15685-
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
15686-
((INSTANCE) == TIM2_NS) || \
15687-
((INSTANCE) == TIM3_NS))
15688+
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
15689+
((INSTANCE) == TIM2_NS) || \
15690+
((INSTANCE) == TIM3_NS) || \
15691+
((INSTANCE) == TIM16_NS) || \
15692+
((INSTANCE) == TIM17_NS))
15693+
15694+
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
15695+
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
15696+
((INSTANCE) == TIM2_NS) || \
15697+
((INSTANCE) == TIM3_NS))
1568815698

1568915699
/****************** TIM Instances : remapping capability **********************/
1569015700
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
@@ -15718,9 +15728,9 @@ typedef struct
1571815728
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS)
1571915729

1572015730
/****************** TIM Instances : supporting synchronization ****************/
15721-
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || \
15722-
((__INSTANCE__) == TIM2_NS) || \
15723-
((__INSTANCE__) == TIM3_NS))
15731+
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
15732+
((INSTANCE) == TIM2_NS) || \
15733+
((INSTANCE) == TIM3_NS))
1572415734

1572515735
/****************************** TSC Instances *********************************/
1572615736
#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS)

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h

Lines changed: 23 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -15069,8 +15069,7 @@ typedef struct
1506915069
((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S))
1507015070

1507115071
/****************** TIM Instances : supporting 32 bits counter ****************/
15072-
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \
15073-
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
15072+
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S))
1507415073

1507515074
/****************** TIM Instances : supporting the break function *************/
1507615075
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
@@ -15256,6 +15255,11 @@ typedef struct
1525615255
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
1525715256
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
1525815257

15258+
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
15259+
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
15260+
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
15261+
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
15262+
1525915263
/****************** TIM Instances : remapping capability **********************/
1526015264
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
1526115265
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
@@ -15289,9 +15293,9 @@ typedef struct
1528915293
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S))
1529015294

1529115295
/****************** TIM Instances : supporting synchronization ****************/
15292-
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \
15293-
((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \
15294-
((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S))
15296+
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \
15297+
((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \
15298+
((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S))
1529515299

1529615300
/****************************** TSC Instances *********************************/
1529715301
#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S))
@@ -15517,8 +15521,7 @@ typedef struct
1551715521
((INSTANCE) == TIM17_NS))
1551815522

1551915523
/****************** TIM Instances : supporting 32 bits counter ****************/
15520-
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \
15521-
((INSTANCE) == TIM3_NS))
15524+
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS)
1552215525

1552315526
/****************** TIM Instances : supporting the break function *************/
1552415527
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
@@ -15700,9 +15703,16 @@ typedef struct
1570015703
((INSTANCE) == TIM3_NS))
1570115704

1570215705
/****************** TIM Instances : supporting OCxREF clear *******************/
15703-
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
15704-
((INSTANCE) == TIM2_NS) || \
15705-
((INSTANCE) == TIM3_NS))
15706+
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
15707+
((INSTANCE) == TIM2_NS) || \
15708+
((INSTANCE) == TIM3_NS) || \
15709+
((INSTANCE) == TIM16_NS) || \
15710+
((INSTANCE) == TIM17_NS))
15711+
15712+
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
15713+
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
15714+
((INSTANCE) == TIM2_NS) || \
15715+
((INSTANCE) == TIM3_NS))
1570615716

1570715717
/****************** TIM Instances : remapping capability **********************/
1570815718
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
@@ -15736,9 +15746,9 @@ typedef struct
1573615746
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS)
1573715747

1573815748
/****************** TIM Instances : supporting synchronization ****************/
15739-
#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || \
15740-
((__INSTANCE__) == TIM2_NS) || \
15741-
((__INSTANCE__) == TIM3_NS))
15749+
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
15750+
((INSTANCE) == TIM2_NS) || \
15751+
((INSTANCE) == TIM3_NS))
1574215752

1574315753
/****************************** TSC Instances *********************************/
1574415754
#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS)

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@
6161
/* #define STM32WBA52xx *//*!< STM32WBA52xx Devices */
6262
/* #define STM32WBA54xx *//*!< STM32WBA54xx Devices */
6363
/* #define STM32WBA55xx *//*!< STM32WBA55xx Devices */
64-
#endif/* !STM32WBA55xx && !STM32WBA52xx ...*/
64+
#endif/* !STM32WBA50xx && !STM32WBA52xx ...*/
6565

6666
/* Tip: To avoid modifying this file each time you need to switch between these
6767
devices, you can define the device in your toolchain compiler preprocessor.
@@ -79,7 +79,7 @@
7979
* @brief CMSIS Device version number
8080
*/
8181
#define__STM32WBA_CMSIS_VERSION_MAIN (0x01U)/*!< [31:24] main version */
82-
#define__STM32WBA_CMSIS_VERSION_SUB1 (0x02U)/*!< [23:16] sub1 version */
82+
#define__STM32WBA_CMSIS_VERSION_SUB1 (0x03U)/*!< [23:16] sub1 version */
8383
#define__STM32WBA_CMSIS_VERSION_SUB2 (0x00U)/*!< [15:8] sub2 version */
8484
#define__STM32WBA_CMSIS_VERSION_RC (0x00U)/*!< [7:0] release candidate */
8585
#define__STM32WBA_CMSIS_VERSION ((__STM32WBA_CMSIS_VERSION_MAIN << 24U)\

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