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62 | 62 | // #define HAL_DCMI_MODULE_ENABLED |
63 | 63 | #defineHAL_DMA_MODULE_ENABLED |
64 | 64 | // #define HAL_DMA2D_MODULE_ENABLED |
65 | | -//#define HAL_ETH_MODULE_ENABLED |
| 65 | +#defineHAL_ETH_MODULE_ENABLED |
66 | 66 | #defineHAL_FLASH_MODULE_ENABLED |
67 | 67 | // #define HAL_NAND_MODULE_ENABLED |
68 | 68 | // #define HAL_NOR_MODULE_ENABLED |
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186 | 186 | /* Definition of the Ethernet driver buffers size and count */ |
187 | 187 | #defineETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE/* buffer size for receive */ |
188 | 188 | #defineETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE/* buffer size for transmit */ |
189 | | -#defineETH_RXBUFNB4U/*4 Rx buffers of size ETH_RX_BUF_SIZE */ |
190 | | -#defineETH_TXBUFNB4U/*4 Tx buffers of size ETH_TX_BUF_SIZE */ |
| 189 | +#defineETH_RXBUFNB(5U)/*5 Rx buffers of size ETH_RX_BUF_SIZE */ |
| 190 | +#defineETH_TXBUFNB(5U)/*5 Tx buffers of size ETH_TX_BUF_SIZE */ |
191 | 191 |
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192 | 192 | /* Section 2: PHY configuration section */ |
193 | | - |
194 | | -/* DP83848 PHY Address*/ |
195 | | -#defineDP83848_PHY_ADDRESS 0x01U |
| 193 | +/* LAN8742A PHY Address*/ |
| 194 | +#defineLAN8742A_PHY_ADDRESS 0x00U |
196 | 195 | /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ |
197 | 196 | #definePHY_RESET_DELAY 0x000000FFU |
198 | 197 | /* PHY Configuration delay */ |
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223 | 222 |
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224 | 223 | /* Section 4: Extended PHY Registers */ |
225 | 224 |
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226 | | -#definePHY_SR ((uint16_t)0x0010)/*!< PHY status register Offset */ |
227 | | -#definePHY_MICR ((uint16_t)0x0011)/*!< MII Interrupt Control Register */ |
228 | | -#definePHY_MISR ((uint16_t)0x0012)/*!< MII Interrupt Status and Misc. Control Register */ |
| 225 | +#definePHY_SR ((uint16_t)0x1F)/*!< PHY special control/ status register Offset */ |
229 | 226 |
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230 | | -#definePHY_LINK_STATUS ((uint16_t)0x0001)/*!< PHY Link mask */ |
231 | | -#definePHY_SPEED_STATUS ((uint16_t)0x0002)/*!< PHY Speed mask */ |
232 | | -#definePHY_DUPLEX_STATUS ((uint16_t)0x0004)/*!< PHY Duplex mask */ |
| 227 | +#definePHY_SPEED_STATUS ((uint16_t)0x0004)/*!< PHY Speed mask */ |
| 228 | +#definePHY_DUPLEX_STATUS ((uint16_t)0x0010)/*!< PHY Duplex mask */ |
233 | 229 |
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234 | | -#definePHY_MICR_INT_EN ((uint16_t)0x0002)/*!< PHY Enable interrupts */ |
235 | | -#definePHY_MICR_INT_OE ((uint16_t)0x0001)/*!< PHY Enable output interrupt events */ |
236 | 230 |
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237 | | -#definePHY_MISR_LINK_INT_EN ((uint16_t)0x0020)/*!< Enable Interrupt on change of link status */ |
238 | | -#definePHY_LINK_INTERRUPT ((uint16_t)0x2000)/*!< PHY link status interrupt mask */ |
| 231 | +#definePHY_ISFR ((uint16_t)0x1D)/*!< PHY Interrupt Source Flag register Offset */ |
| 232 | +#definePHY_IMR ((uint16_t)0x1E)/*!< PHY Interrupt Mask register Offset */ |
| 233 | +#definePHY_ISFR_INT4 ((uint16_t)0x0010)/*!< PHY Link down inturrupt */ |
239 | 234 |
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240 | 235 | /* ################## SPI peripheral configuration ########################## */ |
241 | 236 |
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