|
| 1 | +/* |
| 2 | + ******************************************************************************* |
| 3 | + * Copyright (c) 2021, STMicroelectronics |
| 4 | + * All rights reserved. |
| 5 | + * |
| 6 | + * This software component is licensed by ST under BSD 3-Clause license, |
| 7 | + * the "License"; You may not use this file except in compliance with the |
| 8 | + * License. You may obtain a copy of the License at: |
| 9 | + * opensource.org/licenses/BSD-3-Clause |
| 10 | + * |
| 11 | + ******************************************************************************* |
| 12 | +*/ |
| 13 | +#if defined(ARDUINO_STM32WB5MM_DK) |
| 14 | +#include"pins_arduino.h" |
| 15 | +#include"lock_resource.h" |
| 16 | + |
| 17 | +// Digital PinName array |
| 18 | +const PinName digitalPin[] = { |
| 19 | + PC_0,// D0/A9 |
| 20 | + PB_5,// D1 |
| 21 | + PD_12,// D2 |
| 22 | + PD_14,// D3 |
| 23 | + PE_4,// D4 |
| 24 | + PB_10,// D5 |
| 25 | + PE_0,// D6 |
| 26 | + PB_2,// D7 |
| 27 | + PD_13,// D8 |
| 28 | + PD_15,// D9 |
| 29 | + PA_4,// D10/A10 |
| 30 | + PA_7,// D11/A11 |
| 31 | + PB_4,// D12 |
| 32 | + PA_1,// D13/A12 |
| 33 | + PA_10,// D14 |
| 34 | + PB_8,// D15 |
| 35 | + PC_3,// D16/A0 |
| 36 | + PA_2,// D17/A1 |
| 37 | + PA_5,// D18/A2 |
| 38 | + PC_1,// D19/A3 |
| 39 | + PC_4,// D20/A4 |
| 40 | + PC_5,// D21/A5 |
| 41 | + PD_0,// D22 |
| 42 | + PA_6,// D23/A6 |
| 43 | + PD_4,// D24 |
| 44 | + PC_2,// D25/A7 |
| 45 | + PD_1,// D26 |
| 46 | + PB_12,// D27 |
| 47 | + PB_15,// D28 |
| 48 | + PB_14,// D29 |
| 49 | + PE_3,// D30 |
| 50 | + PD_8,// D31 |
| 51 | + PA_0,// D32/A8 |
| 52 | + PA_15,// D33 |
| 53 | + PC_11,// D34 |
| 54 | + PC_10,// D35 |
| 55 | + PC_12,// D36 |
| 56 | + PC_13,// D37 |
| 57 | + PB_6,// D38 |
| 58 | + PB_7,// D39 |
| 59 | + PA_11,// D40 |
| 60 | + PA_12,// D41 |
| 61 | + PD_3,// D42 |
| 62 | + PA_3,// D43 |
| 63 | + PB_9,// D44 |
| 64 | + PD_5,// D45 |
| 65 | + PD_6,// D46 |
| 66 | + PD_7,// D47 |
| 67 | + PA_8,// D48 |
| 68 | + PA_9,// D49 |
| 69 | + PC_6,// D50 |
| 70 | + PC_7,// D51 |
| 71 | + PD_10,// D52 |
| 72 | + PD_11,// D53 |
| 73 | + PC_8,// D54 |
| 74 | + PC_9,// D55 |
| 75 | + PH_0,// D56 |
| 76 | + PB_11,// D57 |
| 77 | + PB_13,// D58 |
| 78 | + PD_2,// D59 |
| 79 | + PD_9,// D60 |
| 80 | + PE_1,// D61 |
| 81 | + PA_13,// D62 |
| 82 | + PA_14,// D63 |
| 83 | + PB_3,// D64 |
| 84 | + PE_2,// D65 |
| 85 | + PH_1,// D66 |
| 86 | + PH_3// D67 |
| 87 | +}; |
| 88 | + |
| 89 | +// Analog (Ax) pin number array |
| 90 | +constuint32_t analogInputPin[] = { |
| 91 | +16,// A0, PC3 |
| 92 | +17,// A1, PA2 |
| 93 | +18,// A2, PA5 |
| 94 | +19,// A3, PC1 |
| 95 | +20,// A4, PC4 |
| 96 | +21,// A5, PC5 |
| 97 | +23,// A6, PA6 |
| 98 | +25,// A7, PC2 |
| 99 | +32,// A8, PA0 |
| 100 | +0,// A9, PC0 |
| 101 | +10,// A10, PA4 |
| 102 | +11,// A11, PA7 |
| 103 | +13// A12, PA1 |
| 104 | +}; |
| 105 | + |
| 106 | +// ---------------------------------------------------------------------------- |
| 107 | +#ifdef __cplusplus |
| 108 | +extern"C" { |
| 109 | +#endif |
| 110 | + |
| 111 | +/** |
| 112 | + * @brief System Clock Configuration |
| 113 | + * @param None |
| 114 | + * @retval None |
| 115 | +*/ |
| 116 | +WEAKvoidSystemClock_Config(void) |
| 117 | +{ |
| 118 | + RCC_OscInitTypeDef RCC_OscInitStruct = {}; |
| 119 | + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; |
| 120 | + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; |
| 121 | + |
| 122 | +/* This prevents concurrent access to RCC registers by CPU2 (M0+)*/ |
| 123 | +hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY); |
| 124 | + |
| 125 | +/** Configure LSE Drive Capability |
| 126 | +*/ |
| 127 | +HAL_PWR_EnableBkUpAccess(); |
| 128 | +__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); |
| 129 | +/** Configure the main internal regulator output voltage |
| 130 | +*/ |
| 131 | +__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
| 132 | + |
| 133 | +/* This prevents the CPU2 (M0+) to disable the HSI48 oscillator*/ |
| 134 | +hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY); |
| 135 | + |
| 136 | +/** Initializes the RCC Oscillators according to the specified parameters |
| 137 | + * in the RCC_OscInitTypeDef structure. |
| 138 | +*/ |
| 139 | + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI |
| 140 | + | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; |
| 141 | + RCC_OscInitStruct.HSEState = RCC_HSE_ON; |
| 142 | + RCC_OscInitStruct.LSEState = RCC_LSE_ON; |
| 143 | + RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| 144 | + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; |
| 145 | + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
| 146 | + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| 147 | + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| 148 | + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; |
| 149 | + RCC_OscInitStruct.PLL.PLLN =8; |
| 150 | + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; |
| 151 | + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; |
| 152 | + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; |
| 153 | +if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
| 154 | +Error_Handler(); |
| 155 | + } |
| 156 | +/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers |
| 157 | +*/ |
| 158 | + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2 |
| 159 | + | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
| 160 | + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |
| 161 | + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
| 162 | + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
| 163 | + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; |
| 164 | + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; |
| 165 | + RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2; |
| 166 | + RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; |
| 167 | + |
| 168 | +if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { |
| 169 | +Error_Handler(); |
| 170 | + } |
| 171 | +/** Initializes the peripherals clocks |
| 172 | +*/ |
| 173 | +/* RNG needs to be configured like in M0 core, i.e. with HSI48*/ |
| 174 | + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP |
| 175 | + | RCC_PERIPHCLK_CLK48SEL | RCC_PERIPHCLK_USB |
| 176 | + | RCC_PERIPHCLK_RNG; |
| 177 | + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; |
| 178 | + PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; |
| 179 | + PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE; |
| 180 | + PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE; |
| 181 | + PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0; |
| 182 | +if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { |
| 183 | +Error_Handler(); |
| 184 | + } |
| 185 | + |
| 186 | +LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA); |
| 187 | +LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40); |
| 188 | +LL_PWR_SMPS_Enable(); |
| 189 | + |
| 190 | +/* Select HSI as system clock source after Wake Up from Stop mode*/ |
| 191 | +LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI); |
| 192 | + |
| 193 | +hsem_unlock(CFG_HW_RCC_SEMID); |
| 194 | +} |
| 195 | + |
| 196 | +#ifdef __cplusplus |
| 197 | +} |
| 198 | +#endif |
| 199 | +#endif/* ARDUINO_STM32WB5MM_DK*/ |