4040 ******************************************************************************
4141 * @attention
4242 *
43- *<h2><center>© Copyright (c) 2016 STMicroelectronics.
44- * All rights reserved.</center></h2>
43+ * Copyright (c) 2016 STMicroelectronics.
44+ * All rights reserved.
4545 *
4646 * This software component is licensed by ST under BSD 3-Clause license,
4747 * the "License"; You may not use this file except in compliance with the
@@ -212,6 +212,8 @@ void SystemInit(void)
212212 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
213213 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
214214 *
215+ * - If SYSCLK source is HSI48, SystemCoreClock will contain the HSI48_VALUE(***)
216+ *
215217 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
216218 * 8 MHz) but the real value may vary depending on the variations
217219 * in voltage and temperature.
@@ -221,6 +223,10 @@ void SystemInit(void)
221223 * is same as the real frequency of the crystal used. Otherwise, this function
222224 * may have wrong result.
223225 *
226+ * (***) HSI48_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
227+ * 48 MHz) but the real value may vary depending on the variations
228+ * in voltage and temperature.
229+ *
224230 * - The result of this function could be not correct when using fractional
225231 * value for HSE crystal.
226232 *
@@ -254,13 +260,13 @@ void SystemCoreClockUpdate (void)
254260/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
255261SystemCoreClock = (HSE_VALUE /predivfactor )* pllmull ;
256262 }
257- #if defined(STM32F042x6 )|| defined(STM32F048xx )|| defined(STM32F072xB )|| defined(STM32F078xx )|| defined(STM32F091xC )|| defined(STM32F098xx )
263+ #if defined(STM32F042x6 )|| defined(STM32F048xx )|| defined(STM32F071xB ) || defined( STM32F072xB )|| defined(STM32F078xx )|| defined(STM32F091xC )|| defined(STM32F098xx )
258264else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV )
259265 {
260266/* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
261267SystemCoreClock = (HSI48_VALUE /predivfactor )* pllmull ;
262268 }
263- #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
269+ #endif /* STM32F042x6 || STM32F048xx ||STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
264270else
265271 {
266272#if defined(STM32F042x6 )|| defined(STM32F048xx )|| defined(STM32F070x6 ) \