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Commitc00f262

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[PNUCLEO_WB55RG] BLE support configuration
Enable IPCC HAL module which transport the HCI commandover the Shared Mem.Update clock configuration for BLE on this nucleo_wb55rgManage OTP to access the device bd addressSigned-off-by: Francois Ramu <francois.ramu@st.com>
1 parentbee8561 commitc00f262

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3 files changed

+109
-32
lines changed

3 files changed

+109
-32
lines changed

‎variants/PNUCLEO_WB55RG/otp.h

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
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/**
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******************************************************************************
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* @file otp.h
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* @author MCD Application Team
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* @brief OTP manager interface
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******************************************************************************
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* @attention
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*
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* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
22+
#ifndef__OTP_H
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#define__OTP_H
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25+
#ifdef__cplusplus
26+
extern"C" {
27+
#endif
28+
29+
typedefstruct__packed {
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uint8_tbd_address[6];
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uint8_thse_tuning;
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uint8_tid;
33+
}OTP_ID0_t;
34+
#error
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/* Exported constants --------------------------------------------------------*/
36+
#defineCFG_OTP_BASE_ADDRESS OTP_AREA_BASE
37+
38+
#defineCFG_OTP_END_ADDRESS OTP_AREA_END_ADDR
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#ifdef__cplusplus
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}
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#endif
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#endif/*__OTP_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

‎variants/PNUCLEO_WB55RG/variant.cpp

Lines changed: 61 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
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*/
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1919
#include"pins_arduino.h"
20+
#include"otp.h"
2021

2122
#ifdef __cplusplus
2223
extern"C" {
@@ -88,6 +89,36 @@ const PinName digitalPin[] = {
8889
extern"C" {
8990
#endif
9091

92+
staticuint8_t *OTP_Read(uint8_t id)
93+
{
94+
uint8_t *p_id;
95+
96+
p_id = (uint8_t *)(CFG_OTP_END_ADDRESS -7) ;
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98+
while (((*(p_id +7)) != id) && (p_id != (uint8_t *)CFG_OTP_BASE_ADDRESS)) {
99+
p_id -=8 ;
100+
}
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102+
if ((*(p_id +7)) != id) {
103+
p_id =0 ;
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}
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return p_id ;
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}
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109+
staticvoidConfig_HSE(void)
110+
{
111+
OTP_ID0_t *p_otp;
112+
113+
/**
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* Read HSE_Tuning from OTP
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*/
116+
p_otp = (OTP_ID0_t *)OTP_Read(0);
117+
if (p_otp) {
118+
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
119+
}
120+
}
121+
91122
/**
92123
* @brief System Clock Configuration
93124
* @param None
@@ -99,60 +130,58 @@ WEAK void SystemClock_Config(void)
99130
RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
100131
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
101132

102-
/* Configure LSE Drive Capability*/
133+
Config_HSE();
134+
103135
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
104-
/* Configure the main internal regulator output voltage*/
105136
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
106-
/* Initializes the CPU, AHB and APB busses clocks*/
107-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
108-
| RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
137+
138+
/* Initializes the CPU, AHB and APB busses clocks*/
139+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48
140+
| RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
109141
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
110-
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
111142
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
112-
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
143+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
144+
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
113145
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
114-
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
115-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
116-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
117-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
118-
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
119-
RCC_OscInitStruct.PLL.PLLN =32;
120-
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
121-
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
122-
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
146+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
123147
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
124148
Error_Handler();
125149
}
150+
126151
/* Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers*/
127152
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
128153
| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
129154
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
130-
RCC_ClkInitStruct.SYSCLKSource =RCC_SYSCLKSOURCE_PLLCLK;
155+
RCC_ClkInitStruct.SYSCLKSource =RCC_SYSCLKSOURCE_HSE;
131156
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
132157
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
133158
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
134-
RCC_ClkInitStruct.AHBCLK2Divider =RCC_SYSCLK_DIV2;
159+
RCC_ClkInitStruct.AHBCLK2Divider =RCC_SYSCLK_DIV1;
135160
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
136-
137-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
161+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
138162
Error_Handler();
139163
}
140-
/* Initializes the peripherals clocks*/
141-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_USB;
142-
PeriphClkInitStruct.PLLSAI1.PLLN =24;
143-
PeriphClkInitStruct.PLLSAI1.PLLP = RCC_PLLP_DIV2;
144-
PeriphClkInitStruct.PLLSAI1.PLLQ = RCC_PLLQ_DIV2;
145-
PeriphClkInitStruct.PLLSAI1.PLLR = RCC_PLLR_DIV2;
146-
PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK;
147-
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
148-
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI;
149-
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
150164

165+
/* Initializes the peripherals clocks*/
166+
/* RNG needs to be configured like in M0 core, i.e. with HSI48*/
167+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP
168+
| RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB;
169+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
170+
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
171+
PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
172+
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
173+
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
151174
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
152175
Error_Handler();
153176
}
154-
/* Enable MSI Auto calibration*/
155-
HAL_RCCEx_EnableMSIPLLMode();
177+
178+
LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
179+
LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
180+
LL_PWR_SMPS_Enable();
181+
182+
/* Select HSI as system clock source after Wake Up from Stop mode*/
183+
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
184+
156185
}
157186

158187
#ifdef __cplusplus

‎variants/PNUCLEO_WB55RG/variant.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,8 @@ extern "C" {
120120
// for EEPROM emulation to the last 512k pages.
121121
#defineFLASH_PAGE_NUMBER 127
122122

123+
#defineHAL_IPCC_MODULE_ENABLED
124+
123125
#ifdef__cplusplus
124126
}// extern "C"
125127
#endif

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