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Commit9fb5081

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emoninet2fpistm
andauthored
variant: add STM32L433RC, STM32L433RB and STM32L443RC support (#2033)
* add STM32L433RC, STM32L433RB and STM32L443RC supportSigned-off-by: Habibur Rahman <hr19392@outlook.com>Co-authored-by: Frederic Pillon <frederic.pillon@st.com>
1 parentabce8f6 commit9fb5081

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4 files changed

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‎README.md

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Original file line numberDiff line numberDiff line change
@@ -641,6 +641,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
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|:green_heart:| STM32L433CBT<br>STM32L433CCT| Generic Board|*2.1.0*||
642642
|:green_heart:| STM32L433CBU<br>STM32L433CCU| Generic Board|*2.1.0*||
643643
|:green_heart:| STM32L443CC<br>STM32L443CC| Generic Board|*2.1.0*||
644+
|:yellow_heart:| STM32L433RC<br>STM32L443RC<br>STM32L433RB| Generic Board|**2.6.0**||
644645
|:green_heart:| STM32L433RC-P| Generic Board|*2.0.0*||
645646
|:green_heart:| STM32L452RC<br>STM32L452RE<br>STM32L462RE| Generic Board|*2.0.0*||
646647
|:green_heart:| STM32L452RE|[Leafony AP03](https://docs.leafony.com/en/docs/leaf/processor/ap03)|*2.4.0*|

‎boards.txt

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Original file line numberDiff line numberDiff line change
@@ -9239,6 +9239,78 @@ GenL4.menu.pnum.GENERIC_L433CCUX.build.board=GENERIC_L433CCUX
92399239
GenL4.menu.pnum.GENERIC_L433CCUX.build.product_line=STM32L433xx
92409240
GenL4.menu.pnum.GENERIC_L433CCUX.build.variant=STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)
92419241

9242+
# Generic L433RBIx
9243+
GenL4.menu.pnum.GENERIC_L433RBIX=Generic L433RBIx
9244+
GenL4.menu.pnum.GENERIC_L433RBIX.upload.maximum_size=131072
9245+
GenL4.menu.pnum.GENERIC_L433RBIX.upload.maximum_data_size=65536
9246+
GenL4.menu.pnum.GENERIC_L433RBIX.build.board=GENERIC_L433RBIX
9247+
GenL4.menu.pnum.GENERIC_L433RBIX.build.product_line=STM32L433xx
9248+
GenL4.menu.pnum.GENERIC_L433RBIX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9249+
9250+
# Generic L433RCIx
9251+
GenL4.menu.pnum.GENERIC_L433RCIX=Generic L433RCIx
9252+
GenL4.menu.pnum.GENERIC_L433RCIX.upload.maximum_size=262144
9253+
GenL4.menu.pnum.GENERIC_L433RCIX.upload.maximum_data_size=65536
9254+
GenL4.menu.pnum.GENERIC_L433RCIX.build.board=GENERIC_L433RCIX
9255+
GenL4.menu.pnum.GENERIC_L433RCIX.build.product_line=STM32L433xx
9256+
GenL4.menu.pnum.GENERIC_L433RCIX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9257+
9258+
# Generic L433RBTx
9259+
GenL4.menu.pnum.GENERIC_L433RBTX=Generic L433RBTx
9260+
GenL4.menu.pnum.GENERIC_L433RBTX.upload.maximum_size=131072
9261+
GenL4.menu.pnum.GENERIC_L433RBTX.upload.maximum_data_size=65536
9262+
GenL4.menu.pnum.GENERIC_L433RBTX.build.board=GENERIC_L433RBTX
9263+
GenL4.menu.pnum.GENERIC_L433RBTX.build.product_line=STM32L433xx
9264+
GenL4.menu.pnum.GENERIC_L433RBTX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9265+
9266+
# Generic L433RCTx
9267+
GenL4.menu.pnum.GENERIC_L433RCTX=Generic L433RCTx
9268+
GenL4.menu.pnum.GENERIC_L433RCTX.upload.maximum_size=262144
9269+
GenL4.menu.pnum.GENERIC_L433RCTX.upload.maximum_data_size=65536
9270+
GenL4.menu.pnum.GENERIC_L433RCTX.build.board=GENERIC_L433RCTX
9271+
GenL4.menu.pnum.GENERIC_L433RCTX.build.product_line=STM32L433xx
9272+
GenL4.menu.pnum.GENERIC_L433RCTX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9273+
9274+
# Generic L433RBYx
9275+
GenL4.menu.pnum.GENERIC_L433RBYX=Generic L433RBYx
9276+
GenL4.menu.pnum.GENERIC_L433RBYX.upload.maximum_size=131072
9277+
GenL4.menu.pnum.GENERIC_L433RBYX.upload.maximum_data_size=65536
9278+
GenL4.menu.pnum.GENERIC_L433RBYX.build.board=GENERIC_L433RBYX
9279+
GenL4.menu.pnum.GENERIC_L433RBYX.build.product_line=STM32L433xx
9280+
GenL4.menu.pnum.GENERIC_L433RBYX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9281+
9282+
# Generic L433RCYx
9283+
GenL4.menu.pnum.GENERIC_L433RCYX=Generic L433RCYx
9284+
GenL4.menu.pnum.GENERIC_L433RCYX.upload.maximum_size=262144
9285+
GenL4.menu.pnum.GENERIC_L433RCYX.upload.maximum_data_size=65536
9286+
GenL4.menu.pnum.GENERIC_L433RCYX.build.board=GENERIC_L433RCYX
9287+
GenL4.menu.pnum.GENERIC_L433RCYX.build.product_line=STM32L433xx
9288+
GenL4.menu.pnum.GENERIC_L433RCYX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9289+
9290+
# Generic L443RCIx
9291+
GenL4.menu.pnum.GENERIC_L443RCIX=Generic L443RCIx
9292+
GenL4.menu.pnum.GENERIC_L443RCIX.upload.maximum_size=262144
9293+
GenL4.menu.pnum.GENERIC_L443RCIX.upload.maximum_data_size=65536
9294+
GenL4.menu.pnum.GENERIC_L443RCIX.build.board=GENERIC_L443RCIX
9295+
GenL4.menu.pnum.GENERIC_L443RCIX.build.product_line=STM32L443xx
9296+
GenL4.menu.pnum.GENERIC_L443RCIX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9297+
9298+
# Generic L443RCTx
9299+
GenL4.menu.pnum.GENERIC_L443RCTX=Generic L443RCTx
9300+
GenL4.menu.pnum.GENERIC_L443RCTX.upload.maximum_size=262144
9301+
GenL4.menu.pnum.GENERIC_L443RCTX.upload.maximum_data_size=65536
9302+
GenL4.menu.pnum.GENERIC_L443RCTX.build.board=GENERIC_L443RCTX
9303+
GenL4.menu.pnum.GENERIC_L443RCTX.build.product_line=STM32L443xx
9304+
GenL4.menu.pnum.GENERIC_L443RCTX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9305+
9306+
# Generic L443RCYx
9307+
GenL4.menu.pnum.GENERIC_L443RCYX=Generic L443RCYx
9308+
GenL4.menu.pnum.GENERIC_L443RCYX.upload.maximum_size=262144
9309+
GenL4.menu.pnum.GENERIC_L443RCYX.upload.maximum_data_size=65536
9310+
GenL4.menu.pnum.GENERIC_L443RCYX.build.board=GENERIC_L443RCYX
9311+
GenL4.menu.pnum.GENERIC_L443RCYX.build.product_line=STM32L443xx
9312+
GenL4.menu.pnum.GENERIC_L443RCYX.build.variant=STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)
9313+
92429314
# Generic L433RCTxP
92439315
GenL4.menu.pnum.GENERIC_L433RCTXP=Generic L433RCTxP
92449316
GenL4.menu.pnum.GENERIC_L433RCTXP.upload.maximum_size=262144

‎variants/STM32L4xx/L433R(B-C)(I-T-Y)_L443RC(I-T-Y)/generic_clock.c

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@@ -24,8 +24,53 @@
2424
*/
2525
WEAKvoidSystemClock_Config(void)
2626
{
27-
/* SystemClock_Config can be generated by STM32CubeMX */
28-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
27+
RCC_OscInitTypeDefRCC_OscInitStruct= {};
28+
RCC_ClkInitTypeDefRCC_ClkInitStruct= {};
29+
RCC_PeriphCLKInitTypeDefPeriphClkInit= {};
30+
31+
/** Configure the main internal regulator output voltage
32+
*/
33+
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1)!=HAL_OK) {
34+
Error_Handler();
35+
}
36+
37+
/** Initializes the RCC Oscillators according to the specified parameters
38+
* in the RCC_OscInitTypeDef structure.
39+
*/
40+
RCC_OscInitStruct.OscillatorType=RCC_OSCILLATORTYPE_HSI48 |RCC_OSCILLATORTYPE_MSI;
41+
RCC_OscInitStruct.HSI48State=RCC_HSI48_ON;
42+
RCC_OscInitStruct.MSIState=RCC_MSI_ON;
43+
RCC_OscInitStruct.MSICalibrationValue=0;
44+
RCC_OscInitStruct.MSIClockRange=RCC_MSIRANGE_6;
45+
RCC_OscInitStruct.PLL.PLLState=RCC_PLL_ON;
46+
RCC_OscInitStruct.PLL.PLLSource=RCC_PLLSOURCE_MSI;
47+
RCC_OscInitStruct.PLL.PLLM=1;
48+
RCC_OscInitStruct.PLL.PLLN=40;
49+
RCC_OscInitStruct.PLL.PLLP=RCC_PLLP_DIV7;
50+
RCC_OscInitStruct.PLL.PLLQ=RCC_PLLQ_DIV2;
51+
RCC_OscInitStruct.PLL.PLLR=RCC_PLLR_DIV2;
52+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct)!=HAL_OK) {
53+
Error_Handler();
54+
}
55+
56+
/** Initializes the CPU, AHB and APB buses clocks
57+
*/
58+
RCC_ClkInitStruct.ClockType=RCC_CLOCKTYPE_HCLK |RCC_CLOCKTYPE_SYSCLK
59+
|RCC_CLOCKTYPE_PCLK1 |RCC_CLOCKTYPE_PCLK2;
60+
RCC_ClkInitStruct.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK;
61+
RCC_ClkInitStruct.AHBCLKDivider=RCC_SYSCLK_DIV1;
62+
RCC_ClkInitStruct.APB1CLKDivider=RCC_HCLK_DIV1;
63+
RCC_ClkInitStruct.APB2CLKDivider=RCC_HCLK_DIV1;
64+
65+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct,FLASH_LATENCY_4)!=HAL_OK) {
66+
Error_Handler();
67+
}
68+
69+
PeriphClkInit.PeriphClockSelection=RCC_PERIPHCLK_USB;
70+
PeriphClkInit.UsbClockSelection=RCC_USBCLKSOURCE_HSI48;
71+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit)!=HAL_OK) {
72+
Error_Handler();
73+
}
2974
}
3075

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#endif/* ARDUINO_GENERIC_* */
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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,186 @@
1+
/*
2+
******************************************************************************
3+
**
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** @file : LinkerScript.ld
5+
**
6+
** @author : Auto-generated by STM32CubeIDE
7+
**
8+
** @brief : Linker script for STM32L433RCTx Device from STM32L4 series
9+
** 256Kbytes FLASH
10+
** 64Kbytes RAM
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** 16Kbytes RAM2
12+
**
13+
** Set heap size, stack size and stack location according
14+
** to application requirements.
15+
**
16+
** Set memory bank area and size if external memory is used
17+
**
18+
** Target : STMicroelectronics STM32
19+
**
20+
** Distribution: The file is distributed as is, without any warranty
21+
** of any kind.
22+
**
23+
******************************************************************************
24+
** @attention
25+
**
26+
** Copyright (c) 2023 STMicroelectronics.
27+
** All rights reserved.
28+
**
29+
** This software is licensed under terms that can be found in the LICENSE file
30+
** in the root directory of this software component.
31+
** If no LICENSE file comes with this software, it is provided AS-IS.
32+
**
33+
******************************************************************************
34+
*/
35+
36+
/* Entry Point */
37+
ENTRY(Reset_Handler)
38+
39+
/* Highest address of the user mode stack */
40+
_estack =ORIGIN(RAM) +LENGTH(RAM); /* end of "RAM" Ram type memory */
41+
42+
_Min_Heap_Size = 0x200; /* required amount of heap */
43+
_Min_Stack_Size = 0x400; /* required amount of stack */
44+
45+
/* Memories definition */
46+
MEMORY
47+
{
48+
RAM (xrw) :ORIGIN = 0x20000000,LENGTH = LD_MAX_DATA_SIZE
49+
FLASH (rx) :ORIGIN = 0x8000000 + LD_FLASH_OFFSET,LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
50+
}
51+
52+
/* Sections */
53+
SECTIONS
54+
{
55+
/* The startup code into "FLASH" Rom type memory */
56+
.isr_vector :
57+
{
58+
. =ALIGN(4);
59+
KEEP(*(.isr_vector)) /* Startup code */
60+
. =ALIGN(4);
61+
} >FLASH
62+
63+
/* The program code and other data into "FLASH" Rom type memory */
64+
.text :
65+
{
66+
. =ALIGN(4);
67+
*(.text) /* .text sections (code) */
68+
*(.text*) /* .text* sections (code) */
69+
*(.glue_7) /* glue arm to thumb code */
70+
*(.glue_7t) /* glue thumb to arm code */
71+
*(.eh_frame)
72+
73+
KEEP (*(.init))
74+
KEEP (*(.fini))
75+
76+
. =ALIGN(4);
77+
_etext = .; /* define a global symbols at end of code */
78+
} >FLASH
79+
80+
/* Constant data into "FLASH" Rom type memory */
81+
.rodata :
82+
{
83+
. =ALIGN(4);
84+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
85+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
86+
. =ALIGN(4);
87+
} >FLASH
88+
89+
.ARM.extab : {
90+
. =ALIGN(4);
91+
*(.ARM.extab* .gnu.linkonce.armextab.*)
92+
. =ALIGN(4);
93+
} >FLASH
94+
95+
.ARM : {
96+
. =ALIGN(4);
97+
__exidx_start = .;
98+
*(.ARM.exidx*)
99+
__exidx_end = .;
100+
. =ALIGN(4);
101+
} >FLASH
102+
103+
.preinit_array :
104+
{
105+
. =ALIGN(4);
106+
PROVIDE_HIDDEN (__preinit_array_start = .);
107+
KEEP (*(.preinit_array*))
108+
PROVIDE_HIDDEN (__preinit_array_end = .);
109+
. =ALIGN(4);
110+
} >FLASH
111+
112+
.init_array :
113+
{
114+
. =ALIGN(4);
115+
PROVIDE_HIDDEN (__init_array_start = .);
116+
KEEP (*(SORT(.init_array.*)))
117+
KEEP (*(.init_array*))
118+
PROVIDE_HIDDEN (__init_array_end = .);
119+
. =ALIGN(4);
120+
} >FLASH
121+
122+
.fini_array :
123+
{
124+
. =ALIGN(4);
125+
PROVIDE_HIDDEN (__fini_array_start = .);
126+
KEEP (*(SORT(.fini_array.*)))
127+
KEEP (*(.fini_array*))
128+
PROVIDE_HIDDEN (__fini_array_end = .);
129+
. =ALIGN(4);
130+
} >FLASH
131+
132+
/* Used by the startup to initialize data */
133+
_sidata =LOADADDR(.data);
134+
135+
/* Initialized data sections into "RAM" Ram type memory */
136+
.data :
137+
{
138+
. =ALIGN(4);
139+
_sdata = .; /* create a global symbol at data start */
140+
*(.data) /* .data sections */
141+
*(.data*) /* .data* sections */
142+
*(.RamFunc) /* .RamFunc sections */
143+
*(.RamFunc*) /* .RamFunc* sections */
144+
145+
. =ALIGN(4);
146+
_edata = .; /* define a global symbol at data end */
147+
148+
} >RAM AT> FLASH
149+
150+
/* Uninitialized data section into "RAM" Ram type memory */
151+
. =ALIGN(4);
152+
.bss :
153+
{
154+
/* This is used by the startup in order to initialize the .bss section */
155+
_sbss = .; /* define a global symbol at bss start */
156+
__bss_start__ = _sbss;
157+
*(.bss)
158+
*(.bss*)
159+
*(COMMON)
160+
161+
. =ALIGN(4);
162+
_ebss = .; /* define a global symbol at bss end */
163+
__bss_end__ = _ebss;
164+
} >RAM
165+
166+
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
167+
._user_heap_stack :
168+
{
169+
. =ALIGN(8);
170+
PROVIDE ( end = . );
171+
PROVIDE ( _end = . );
172+
. = . + _Min_Heap_Size;
173+
. = . + _Min_Stack_Size;
174+
. =ALIGN(8);
175+
} >RAM
176+
177+
/* Remove information from the compiler libraries */
178+
/DISCARD/ :
179+
{
180+
libc.a ( * )
181+
libm.a ( * )
182+
libgcc.a ( * )
183+
}
184+
185+
.ARM.attributes 0 : { *(.ARM.attributes) }
186+
}

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