Commit9ca5d48

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Merge pull request#2236 from fpistm/STM32CubeG4_update

chore(G4): update to latest STM32CubeG4 v1.5.2

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`‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h`

Lines changed: 7 additions & 21 deletions

Original file line number	Diff line number	Diff line change
`@@ -699,8 +699,7 @@ typedef struct`
`699`	`699`
`700`	`700`	`typedef struct`
`701`	`701`	`{`
`702`		`- __IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /`
`703`		`- uint32_t RESERVED[16]; /!< Reserved, Address offset: 0x04 to 0x40 /`
	`702`	`+ uint32_t RESERVED[17]; /!< Reserved, Address offset: 0x00 to 0x40 /`
`704`	`703`	`__IO uint32_t PDMCR; /!< SAI PDM control register, Address offset: 0x44 /`
`705`	`704`	`__IO uint32_t PDMDLY; /!< SAI PDM delay register, Address offset: 0x48 /`
`706`	`705`	`} SAI_TypeDef;`
`@@ -1216,7 +1215,7 @@ typedef struct`
`1216`	`1215`	`/******************************************************************************/`
`1217`	`1216`
`1218`	`1217`	`/*`
`1219`		`- * @brief Specific device feature definitions (not present on all devices in the STM32G4serie)`
	`1218`	`+ * @brief Specific device feature definitions (not present on all devices in the STM32G4series)`
`1220`	`1219`	`*/`
`1221`	`1220`	`#define ADC_MULTIMODE_SUPPORT /!< ADC feature available only on specific devices: multimode available on devices with several ADC instances /`
`1222`	`1221`
`@@ -1362,7 +1361,7 @@ typedef struct`
`1362`	`1361`	`#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /!< ADC low power auto wait /`
`1363`	`1362`	`#define ADC_CFGR_ALIGN_Pos (15U)`
`1364`	`1363`	`#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /!< 0x00008000 /`
`1365`		`-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /!< ADC dataalignement /`
	`1364`	`+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /!< ADC dataalignment /`
`1366`	`1365`	`#define ADC_CFGR_DISCEN_Pos (16U)`
`1367`	`1366`	`#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /!< 0x00010000 /`
`1368`	`1367`	`#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /`
`@@ -4063,7 +4062,7 @@ typedef struct`
`4063`	`4062`	`/*************** Bit definition for FDCAN_ENDN register *****************/`
`4064`	`4063`	`#define FDCAN_ENDN_ETV_Pos (0U)`
`4065`	`4064`	`#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /!< 0xFFFFFFFF /`
`4066`		`-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /!<Endiannes Test Value /`
	`4065`	`+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /!<Endianness Test Value /`
`4067`	`4066`
`4068`	`4067`	`/*************** Bit definition for FDCAN_DBTP register *****************/`
`4069`	`4068`	`#define FDCAN_DBTP_DSJW_Pos (0U)`
`@@ -6372,7 +6371,7 @@ typedef struct`
`6372`	`6371`	`#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /!< Offset trimming value (NMOS) /`
`6373`	`6372`	`#define OPAMP_CSR_OUTCAL_Pos (30U)`
`6374`	`6373`	`#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /!< 0x40000000 /`
`6375`		`-#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /!< OPAMPouput status flag /`
	`6374`	`+#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /!< OPAMPoutput status flag /`
`6376`	`6375`	`#define OPAMP_CSR_LOCK_Pos (31U)`
`6377`	`6376`	`#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /!< 0x80000000 /`
`6378`	`6377`	`#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /!< OPAMP control/status register lock /`
`@@ -7225,7 +7224,7 @@ typedef struct`
`7225`	`7224`	`/* */`
`7226`	`7225`	`/******************************************************************************/`
`7227`	`7226`	`/*`
`7228`		`-* @brief Specific device feature definitions (not present on all devices in the STM32G4serie)`
	`7227`	`+* @brief Specific device feature definitions (not present on all devices in the STM32G4series)`
`7229`	`7228`	`*/`
`7230`	`7229`
`7231`	`7230`	`#define RCC_HSI48_SUPPORT`
`@@ -9050,19 +9049,6 @@ typedef struct`
`9050`	`9049`	`/* Serial Audio Interface */`
`9051`	`9050`	`/* */`
`9052`	`9051`	`/******************************************************************************/`
`9053`		`-/****************** Bit definition for SAI_GCR register *****************/`
`9054`		`-#define SAI_GCR_SYNCIN_Pos (0U)`
`9055`		`-#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /!< 0x00000003 /`
`9056`		`-#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /!<SYNCIN[1:0] bits (Synchronization Inputs) /`
`9057`		`-#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /!< 0x00000001 /`
`9058`		`-#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /!< 0x00000002 /`
`9059`		`-`
`9060`		`-#define SAI_GCR_SYNCOUT_Pos (4U)`
`9061`		`-#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /!< 0x00000030 /`
`9062`		`-#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /!<SYNCOUT[1:0] bits (Synchronization Outputs) /`
`9063`		`-#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /!< 0x00000010 /`
`9064`		`-#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /!< 0x00000020 /`
`9065`		`-`
`9066`	`9052`	`/***************** Bit definition for SAI_xCR1 register *****************/`
`9067`	`9053`	`#define SAI_xCR1_MODE_Pos (0U)`
`9068`	`9054`	`#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /!< 0x00000003 /`
`@@ -9403,7 +9389,7 @@ typedef struct`
`9403`	`9389`	`/* */`
`9404`	`9390`	`/******************************************************************************/`
`9405`	`9391`	`/*`
`9406`		`- * @brief Specific device feature definitions (not present on all devices in the STM32G4serie)`
	`9392`	`+ * @brief Specific device feature definitions (not present on all devices in the STM32G4series)`
`9407`	`9393`	`*/`
`9408`	`9394`	`#define SPI_I2S_SUPPORT /!< I2S support /`
`9409`	`9395`

`‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g441xx.h`

Lines changed: 7 additions & 21 deletions

Original file line number	Diff line number	Diff line change
`@@ -700,8 +700,7 @@ typedef struct`
`700`	`700`
`701`	`701`	`typedef struct`
`702`	`702`	`{`
`703`		`- __IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /`
`704`		`- uint32_t RESERVED[16]; /!< Reserved, Address offset: 0x04 to 0x40 /`
	`703`	`+ uint32_t RESERVED[17]; /!< Reserved, Address offset: 0x00 to 0x40 /`
`705`	`704`	`__IO uint32_t PDMCR; /!< SAI PDM control register, Address offset: 0x44 /`
`706`	`705`	`__IO uint32_t PDMDLY; /!< SAI PDM delay register, Address offset: 0x48 /`
`707`	`706`	`} SAI_TypeDef;`
`@@ -1250,7 +1249,7 @@ typedef struct`
`1250`	`1249`	`/******************************************************************************/`
`1251`	`1250`
`1252`	`1251`	`/*`
`1253`		`- * @brief Specific device feature definitions (not present on all devices in the STM32G4serie)`
	`1252`	`+ * @brief Specific device feature definitions (not present on all devices in the STM32G4series)`
`1254`	`1253`	`*/`
`1255`	`1254`	`#define ADC_MULTIMODE_SUPPORT /!< ADC feature available only on specific devices: multimode available on devices with several ADC instances /`
`1256`	`1255`
`@@ -1396,7 +1395,7 @@ typedef struct`
`1396`	`1395`	`#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /!< ADC low power auto wait /`
`1397`	`1396`	`#define ADC_CFGR_ALIGN_Pos (15U)`
`1398`	`1397`	`#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /!< 0x00008000 /`
`1399`		`-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /!< ADC dataalignement /`
	`1398`	`+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /!< ADC dataalignment /`
`1400`	`1399`	`#define ADC_CFGR_DISCEN_Pos (16U)`
`1401`	`1400`	`#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /!< 0x00010000 /`
`1402`	`1401`	`#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /`
`@@ -4284,7 +4283,7 @@ typedef struct`
`4284`	`4283`	`/*************** Bit definition for FDCAN_ENDN register *****************/`
`4285`	`4284`	`#define FDCAN_ENDN_ETV_Pos (0U)`
`4286`	`4285`	`#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /!< 0xFFFFFFFF /`
`4287`		`-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /!<Endiannes Test Value /`
	`4286`	`+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /!<Endianness Test Value /`
`4288`	`4287`
`4289`	`4288`	`/*************** Bit definition for FDCAN_DBTP register *****************/`
`4290`	`4289`	`#define FDCAN_DBTP_DSJW_Pos (0U)`
`@@ -6593,7 +6592,7 @@ typedef struct`
`6593`	`6592`	`#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /!< Offset trimming value (NMOS) /`
`6594`	`6593`	`#define OPAMP_CSR_OUTCAL_Pos (30U)`
`6595`	`6594`	`#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /!< 0x40000000 /`
`6596`		`-#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /!< OPAMPouput status flag /`
	`6595`	`+#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /!< OPAMPoutput status flag /`
`6597`	`6596`	`#define OPAMP_CSR_LOCK_Pos (31U)`
`6598`	`6597`	`#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /!< 0x80000000 /`
`6599`	`6598`	`#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /!< OPAMP control/status register lock /`
`@@ -7446,7 +7445,7 @@ typedef struct`
`7446`	`7445`	`/* */`
`7447`	`7446`	`/******************************************************************************/`
`7448`	`7447`	`/*`
`7449`		`-* @brief Specific device feature definitions (not present on all devices in the STM32G4serie)`
	`7448`	`+* @brief Specific device feature definitions (not present on all devices in the STM32G4series)`
`7450`	`7449`	`*/`
`7451`	`7450`
`7452`	`7451`	`#define RCC_HSI48_SUPPORT`
`@@ -9280,19 +9279,6 @@ typedef struct`
`9280`	`9279`	`/* Serial Audio Interface */`
`9281`	`9280`	`/* */`
`9282`	`9281`	`/******************************************************************************/`
`9283`		`-/****************** Bit definition for SAI_GCR register *****************/`
`9284`		`-#define SAI_GCR_SYNCIN_Pos (0U)`
`9285`		`-#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /!< 0x00000003 /`
`9286`		`-#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /!<SYNCIN[1:0] bits (Synchronization Inputs) /`
`9287`		`-#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /!< 0x00000001 /`
`9288`		`-#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /!< 0x00000002 /`
`9289`		`-`
`9290`		`-#define SAI_GCR_SYNCOUT_Pos (4U)`
`9291`		`-#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /!< 0x00000030 /`
`9292`		`-#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /!<SYNCOUT[1:0] bits (Synchronization Outputs) /`
`9293`		`-#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /!< 0x00000010 /`
`9294`		`-#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /!< 0x00000020 /`
`9295`		`-`
`9296`	`9282`	`/***************** Bit definition for SAI_xCR1 register *****************/`
`9297`	`9283`	`#define SAI_xCR1_MODE_Pos (0U)`
`9298`	`9284`	`#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /!< 0x00000003 /`
`@@ -9633,7 +9619,7 @@ typedef struct`
`9633`	`9619`	`/* */`
`9634`	`9620`	`/******************************************************************************/`
`9635`	`9621`	`/*`
`9636`		`- * @brief Specific device feature definitions (not present on all devices in the STM32G4serie)`
	`9622`	`+ * @brief Specific device feature definitions (not present on all devices in the STM32G4series)`
`9637`	`9623`	`*/`
`9638`	`9624`	`#define SPI_I2S_SUPPORT /!< I2S support /`
`9639`	`9625`

`‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g471xx.h`

Lines changed: 7 additions & 21 deletions

Original file line number	Diff line number	Diff line change
`@@ -757,8 +757,7 @@ typedef struct`
`757`	`757`
`758`	`758`	`typedef struct`
`759`	`759`	`{`
`760`		`- __IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /`
`761`		`- uint32_t RESERVED[16]; /!< Reserved, Address offset: 0x04 to 0x40 /`
	`760`	`+ uint32_t RESERVED[17]; /!< Reserved, Address offset: 0x00 to 0x40 /`
`762`	`761`	`__IO uint32_t PDMCR; /!< SAI PDM control register, Address offset: 0x44 /`
`763`	`762`	`__IO uint32_t PDMDLY; /!< SAI PDM delay register, Address offset: 0x48 /`
`764`	`763`	`} SAI_TypeDef;`
`@@ -1307,7 +1306,7 @@ typedef struct`
`1307`	`1306`	`/******************************************************************************/`
`1308`	`1307`
`1309`	`1308`	`/*`
`1310`		`- * @brief Specific device feature definitions (not present on all devices in the STM32G4serie)`
	`1309`	`+ * @brief Specific device feature definitions (not present on all devices in the STM32G4series)`
`1311`	`1310`	`*/`
`1312`	`1311`	`#define ADC_MULTIMODE_SUPPORT /!< ADC feature available only on specific devices: multimode available on devices with several ADC instances /`
`1313`	`1312`
`@@ -1453,7 +1452,7 @@ typedef struct`
`1453`	`1452`	`#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /!< ADC low power auto wait /`
`1454`	`1453`	`#define ADC_CFGR_ALIGN_Pos (15U)`
`1455`	`1454`	`#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /!< 0x00008000 /`
`1456`		`-#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /!< ADC dataalignement /`
	`1455`	`+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /!< ADC dataalignment /`
`1457`	`1456`	`#define ADC_CFGR_DISCEN_Pos (16U)`
`1458`	`1457`	`#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /!< 0x00010000 /`
`1459`	`1458`	`#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /!< ADC group regular sequencer discontinuous mode /`
`@@ -4245,7 +4244,7 @@ typedef struct`
`4245`	`4244`	`/*************** Bit definition for FDCAN_ENDN register *****************/`
`4246`	`4245`	`#define FDCAN_ENDN_ETV_Pos (0U)`
`4247`	`4246`	`#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /!< 0xFFFFFFFF /`
`4248`		`-#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /!<Endiannes Test Value /`
	`4247`	`+#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /!<Endianness Test Value /`
`4249`	`4248`
`4250`	`4249`	`/*************** Bit definition for FDCAN_DBTP register *****************/`
`4251`	`4250`	`#define FDCAN_DBTP_DSJW_Pos (0U)`
`@@ -6607,7 +6606,7 @@ typedef struct`
`6607`	`6606`	`#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /!< Offset trimming value (NMOS) /`
`6608`	`6607`	`#define OPAMP_CSR_OUTCAL_Pos (30U)`
`6609`	`6608`	`#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /!< 0x40000000 /`
`6610`		`-#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /!< OPAMPouput status flag /`
	`6609`	`+#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /!< OPAMPoutput status flag /`
`6611`	`6610`	`#define OPAMP_CSR_LOCK_Pos (31U)`
`6612`	`6611`	`#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /!< 0x80000000 /`
`6613`	`6612`	`#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /!< OPAMP control/status register lock /`
`@@ -7735,7 +7734,7 @@ typedef struct`
`7735`	`7734`	`/* */`
`7736`	`7735`	`/******************************************************************************/`
`7737`	`7736`	`/*`
`7738`		`-* @brief Specific device feature definitions (not present on all devices in the STM32G4serie)`
	`7737`	`+* @brief Specific device feature definitions (not present on all devices in the STM32G4series)`
`7739`	`7738`	`*/`
`7740`	`7739`
`7741`	`7740`	`#define RCC_HSI48_SUPPORT`
`@@ -9714,19 +9713,6 @@ typedef struct`
`9714`	`9713`	`/* Serial Audio Interface */`
`9715`	`9714`	`/* */`
`9716`	`9715`	`/******************************************************************************/`
`9717`		`-/****************** Bit definition for SAI_GCR register *****************/`
`9718`		`-#define SAI_GCR_SYNCIN_Pos (0U)`
`9719`		`-#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /!< 0x00000003 /`
`9720`		`-#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /!<SYNCIN[1:0] bits (Synchronization Inputs) /`
`9721`		`-#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /!< 0x00000001 /`
`9722`		`-#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /!< 0x00000002 /`
`9723`		`-`
`9724`		`-#define SAI_GCR_SYNCOUT_Pos (4U)`
`9725`		`-#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /!< 0x00000030 /`
`9726`		`-#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /!<SYNCOUT[1:0] bits (Synchronization Outputs) /`
`9727`		`-#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /!< 0x00000010 /`
`9728`		`-#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /!< 0x00000020 /`
`9729`		`-`
`9730`	`9716`	`/***************** Bit definition for SAI_xCR1 register *****************/`
`9731`	`9717`	`#define SAI_xCR1_MODE_Pos (0U)`
`9732`	`9718`	`#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /!< 0x00000003 /`
`@@ -10067,7 +10053,7 @@ typedef struct`
`10067`	`10053`	`/* */`
`10068`	`10054`	`/******************************************************************************/`
`10069`	`10055`	`/*`
`10070`		`- * @brief Specific device feature definitions (not present on all devices in the STM32G4serie)`
	`10056`	`+ * @brief Specific device feature definitions (not present on all devices in the STM32G4series)`
`10071`	`10057`	`*/`
`10072`	`10058`	`#define SPI_I2S_SUPPORT /!< I2S support /`
`10073`	`10059`

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`‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h`

`‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g441xx.h`

`‎system/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g471xx.h`

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