|
22 | 22 | ****************************************************************************** |
23 | 23 | * @attention |
24 | 24 | * |
25 | | -* <h2><center>© Copyright (c) 2017 STMicroelectronics. |
26 | | - * All rights reserved.</center></h2> |
| 25 | + * Copyright (c) 2017 STMicroelectronics. |
| 26 | + * All rights reserved. |
27 | 27 | * |
28 | | - * This software component is licensed by ST under BSD 3-Clause license, |
29 | | - * the "License"; You may not use this file except in compliance with the |
30 | | - * License. You may obtain a copy of the License at: |
31 | | - * opensource.org/licenses/BSD-3-Clause |
| 28 | + * This software is licensed under terms that can be found in the LICENSE file |
| 29 | + * in the root directory of this software component. |
| 30 | + * If no LICENSE file comes with this software, it is provided AS-IS. |
32 | 31 | * |
33 | 32 | ****************************************************************************** |
34 | 33 | */ |
|
87 | 86 | /* #define VECT_TAB_BASE_ADDRESS 0x08000000 */ |
88 | 87 |
|
89 | 88 | /*!< Uncomment the following line if you need to relocate your vector Table |
90 | | - in Sram else user remap will be doneby defaultin Flash. */ |
| 89 | + in Sram else user remap will be done in Flash. */ |
91 | 90 | /* #define VECT_TAB_SRAM */ |
92 | 91 |
|
93 | 92 | #ifndefVECT_TAB_OFFSET |
@@ -235,7 +234,7 @@ void SystemInit(void) |
235 | 234 | */ |
236 | 235 | voidSystemCoreClockUpdate(void) |
237 | 236 | { |
238 | | -uint32_ttmp=0,pllvco=0,pllp=2,pllsource=0,pllm=2; |
| 237 | +uint32_ttmp,pllvco,pllp,pllsource,pllm; |
239 | 238 |
|
240 | 239 | /* Get SYSCLK source -------------------------------------------------------*/ |
241 | 240 | tmp=RCC->CFGR&RCC_CFGR_SWS; |
@@ -761,4 +760,3 @@ void SystemInit_ExtMemCtl(void) |
761 | 760 | /** |
762 | 761 | * @} |
763 | 762 | */ |
764 | | -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |