@@ -1475,9 +1475,9 @@ uint32_t uart_getPCLK(UART_HandleTypeDef *huart)
14751475#elif defined(STM32H7 )
14761476uint32_t sysclk = HAL_RCC_GetSysClockFreq ();
14771477#if defined(STM32H7A3xx )|| defined (STM32H7A3xxQ )|| defined(STM32H7B3xx )|| defined(STM32H7B3xxQ )|| defined(STM32H7B0xx )|| defined(STM32H7B0xxQ )
1478- uint32_t prescaler = (RCC -> CDCFGR2 & ( 0x7UL << 9U )) >>9U ;
1478+ uint32_t prescaler = (RCC -> SRDCFGR & RCC_SRDCFGR_SRDPPRE ) >>RCC_SRDCFGR_SRDPPRE_Pos ;
14791479#else
1480- uint32_t prescaler = (RCC -> D2CFGR & ( 0x7UL << 9U )) >>9U ;
1480+ uint32_t prescaler = (RCC -> D3CFGR & RCC_D3CFGR_D3PPRE ) >>RCC_D3CFGR_D3PPRE_Pos ;
14811481#endif
14821482
14831483uint32_t apb4 = 1 ;
@@ -1521,7 +1521,7 @@ uint32_t uart_getPCLK(UART_HandleTypeDef *huart)
15211521
15221522#if defined(STM32WB0 )
15231523uint32_t sysclk = HAL_RCC_GetSysClockFreq ();
1524- uint32_t ppre2 = (RCC -> CFGR & ( 0x7UL << 11U )) >>11U ;
1524+ uint32_t ppre2 = (RCC -> CFGR & RCC_CFGR_CLKSYSDIV ) >>RCC_CFGR_CLKSYSDIV_Pos ;
15251525uint32_t apb2_div = 1 ;
15261526
15271527switch (ppre2 ) {