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Commit42a4505

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Merge pull request#1764 from TDhaouST/SystemG0_Update_Stm32G0xx
System(g0) update stm32 G0xx HAL Drivers & CMSIS
2 parents7e8ffbf +ff84b23 commit42a4505

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‎system/Drivers/CMSIS/Device/ST/STM32G0xx/Include/stm32g0xx.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@
9090
*/
9191
#define__STM32G0_CMSIS_VERSION_MAIN (0x01U)/*!< [31:24] main version */
9292
#define__STM32G0_CMSIS_VERSION_SUB1 (0x04U)/*!< [23:16] sub1 version */
93-
#define__STM32G0_CMSIS_VERSION_SUB2 (0x02U)/*!< [15:8] sub2 version */
93+
#define__STM32G0_CMSIS_VERSION_SUB2 (0x03U)/*!< [15:8] sub2 version */
9494
#define__STM32G0_CMSIS_VERSION_RC (0x00U)/*!< [7:0] release candidate */
9595
#define__STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
9696
|(__STM32G0_CMSIS_VERSION_SUB1 << 16)\

‎system/Drivers/CMSIS/Device/ST/STM32G0xx/README.md

Lines changed: 1 addition & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -25,15 +25,7 @@ Details about the content of this release are available in the release note [her
2525

2626
##Compatibility information
2727

28-
In this table, you can find the successive versions of this CMSIS Device component, in-line with the corresponding versions of the full MCU package:
29-
30-
CMSIS Device G0 | CMSIS Core | Was delivered in the full MCU package
31-
--------------- | -------------- | -------------------------------------
32-
Tag v1.2.0 | Tag v4.5_cm0 | Tag v1.2.0
33-
Tag v1.3.0 | Tag v5.4.0_cm0 | Tag v1.3.0
34-
Tag v1.4.0 | Tag v5.6.0_cm0 | Tag v1.4.0
35-
Tag v1.4.1 | Tag v5.6.0_cm0 | Tag v1.5.0
36-
Tag v1.4.2 | Tag v5.6.0_cm0 | Tag v1.5.1
28+
It is**crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in[this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeG0/blob/master/Release_Notes.html) release note.
3729

3830
The full**STM32CubeG0** MCU package is available[here](https://github.com/STMicroelectronics/STM32CubeG0).
3931

‎system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
* STM32F3: 2.3.6
77
* STM32F4: 2.6.8
88
* STM32F7: 1.2.7
9-
* STM32G0: 1.4.2
9+
* STM32G0: 1.4.3
1010
* STM32G4: 1.2.2
1111
* STM32H7: 1.10.2
1212
* STM32L0: 1.9.2

‎system/Drivers/STM32G0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 50 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -37,14 +37,16 @@ extern "C" {
3737
#defineAES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
3838
#defineAES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
3939
#defineAES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
40-
#if defined(STM32U5)
40+
#if defined(STM32U5)|| defined(STM32H7)|| defined(STM32MP1)
4141
#defineCRYP_DATATYPE_32B CRYP_NO_SWAP
4242
#defineCRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
4343
#defineCRYP_DATATYPE_8B CRYP_BYTE_SWAP
4444
#defineCRYP_DATATYPE_1B CRYP_BIT_SWAP
45+
#if defined(STM32U5)
4546
#defineCRYP_CCF_CLEAR CRYP_CLEAR_CCF
4647
#defineCRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
4748
#endif/* STM32U5 */
49+
#endif/* STM32U5 || STM32H7 || STM32MP1 */
4850
/**
4951
* @}
5052
*/
@@ -110,6 +112,7 @@ extern "C" {
110112
#defineADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
111113
#defineADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
112114
#endif/* STM32U5 */
115+
113116
/**
114117
* @}
115118
*/
@@ -231,9 +234,11 @@ extern "C" {
231234
/** @defgroup CRC_Aliases CRC API aliases
232235
* @{
233236
*/
237+
#if defined(STM32C0)
238+
#else
234239
#defineHAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse/*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
235240
#defineHAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse/*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
236-
241+
#endif
237242
/**
238243
* @}
239244
*/
@@ -500,7 +505,7 @@ extern "C" {
500505
#defineOB_RDP_LEVEL0 OB_RDP_LEVEL_0
501506
#defineOB_RDP_LEVEL1 OB_RDP_LEVEL_1
502507
#defineOB_RDP_LEVEL2 OB_RDP_LEVEL_2
503-
#if defined(STM32G0)
508+
#if defined(STM32G0)|| defined(STM32C0)
504509
#defineOB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
505510
#defineOB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
506511
#else
@@ -1084,8 +1089,8 @@ extern "C" {
10841089
#defineRTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
10851090

10861091
#defineRTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
1087-
#defineRTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
1088-
#defineRTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
1092+
#defineRTC_TIMESTAMPPIN_PA0RTC_TIMESTAMPPIN_POS1
1093+
#defineRTC_TIMESTAMPPIN_PI8RTC_TIMESTAMPPIN_POS1
10891094
#defineRTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
10901095

10911096
#defineRTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1096,15 +1101,22 @@ extern "C" {
10961101
#defineRTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
10971102
#defineRTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
10981103

1104+
#if defined(STM32F7)
1105+
#defineRTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
1106+
#defineRTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
1107+
#endif/* STM32F7 */
1108+
10991109
#if defined(STM32H7)
11001110
#defineRTC_TAMPCR_TAMPXE RTC_TAMPER_X
11011111
#defineRTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
1112+
#endif/* STM32H7 */
11021113

1114+
#if defined(STM32F7)|| defined(STM32H7)
11031115
#defineRTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
11041116
#defineRTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
11051117
#defineRTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
1106-
#defineRTC_ALL_TAMPER_INTERRUPTRTC_IT_TAMPALL
1107-
#endif/* STM32H7 */
1118+
#defineRTC_ALL_TAMPER_INTERRUPTRTC_IT_TAMP
1119+
#endif/*STM32F7 ||STM32H7 */
11081120

11091121
/**
11101122
* @}
@@ -3411,7 +3423,7 @@ extern "C" {
34113423
#defineRCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
34123424
#defineRCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
34133425

3414-
#if defined(STM32L4)|| defined(STM32WB)|| defined(STM32G0)|| defined(STM32G4)|| defined(STM32L5)|| defined(STM32WL)
3426+
#if defined(STM32L4)|| defined(STM32WB)|| defined(STM32G0)|| defined(STM32G4)|| defined(STM32L5)|| defined(STM32WL)|| defined(STM32C0)
34153427
#defineRCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
34163428
#else
34173429
#defineRCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3524,8 +3536,8 @@ extern "C" {
35243536
#defineRCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
35253537
#defineRCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
35263538
#if defined(STM32U5)
3527-
#defineMSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
3528-
#defineMSISPLLModeSEL RCC_MSISPLL_MODE_SEL
3539+
#defineMSIKPLLModeSELRCC_MSIKPLL_MODE_SEL
3540+
#defineMSISPLLModeSELRCC_MSISPLL_MODE_SEL
35293541
#define__HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
35303542
#define__HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
35313543
#define__HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3541,16 +3553,20 @@ extern "C" {
35413553
#defineRCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
35423554
#defineRCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
35433555
#defineRCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
3544-
#define__HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3545-
#define__HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3546-
#define__HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3547-
#define__HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3548-
#define__HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3549-
#define__HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3550-
#define__HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3551-
#define__HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3552-
#define__HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
3553-
#endif
3556+
#define__HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3557+
#define__HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3558+
#define__HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3559+
#define__HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3560+
#define__HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3561+
#define__HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3562+
#define__HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3563+
#define__HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3564+
#define__HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
3565+
#define__HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
3566+
#define__HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
3567+
#define__HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
3568+
#defineIS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
3569+
#endif/* STM32U5 */
35543570

35553571
/**
35563572
* @}
@@ -3568,7 +3584,9 @@ extern "C" {
35683584
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
35693585
* @{
35703586
*/
3571-
#if defined (STM32G0)|| defined (STM32L5)|| defined (STM32L412xx)|| defined (STM32L422xx)|| defined (STM32L4P5xx)|| defined (STM32L4Q5xx)|| defined (STM32G4)|| defined (STM32WL)|| defined (STM32U5)
3587+
#if defined (STM32G0)|| defined (STM32L5)|| defined (STM32L412xx)|| defined (STM32L422xx)|| defined (STM32L4P5xx)|| \
3588+
defined (STM32L4Q5xx)|| defined (STM32G4)|| defined (STM32WL)|| defined (STM32U5)|| \
3589+
defined (STM32C0)
35723590
#else
35733591
#define__HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
35743592
#endif
@@ -3632,7 +3650,7 @@ extern "C" {
36323650
#defineSD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
36333651
#defineSD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
36343652

3635-
#if !defined(STM32F1)&& !defined(STM32F2)&& !defined(STM32F4)&& !defined(STM32F7)&& !defined(STM32L1)
3653+
#if !defined(STM32F1)&& !defined(STM32F2)&& !defined(STM32F4)&& !defined(STM32L1)
36363654
#defineeMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
36373655
#defineeMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
36383656
#defineeMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
@@ -3969,6 +3987,16 @@ extern "C" {
39693987
* @}
39703988
*/
39713989

3990+
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
3991+
* @{
3992+
*/
3993+
#if defined (STM32F7)
3994+
#defineART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
3995+
#endif/* STM32F7 */
3996+
/**
3997+
* @}
3998+
*/
3999+
39724000
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
39734001
* @{
39744002
*/

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