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Commit1621139

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Merge pull request#2858 from fpistm/stm32cubel4_update
chore(l4): update to latest STM32CubeL4 v1.18.2
2 parents27aca29 +a86e566 commit1621139

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116 files changed

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‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h‎

Lines changed: 12 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -717,21 +717,17 @@ typedef struct
717717

718718
typedef struct
719719
{
720-
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
721-
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
722-
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
723-
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
724-
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
725-
uint16_t RESERVED2; /*!< Reserved, 0x12 */
726-
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
727-
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
728-
uint16_t RESERVED3; /*!< Reserved, 0x1A */
729-
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
730-
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
731-
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
732-
uint16_t RESERVED4; /*!< Reserved, 0x26 */
733-
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
734-
uint16_t RESERVED5; /*!< Reserved, 0x2A */
720+
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
721+
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
722+
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
723+
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
724+
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
725+
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
726+
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
727+
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
728+
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
729+
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
730+
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
735731
} USART_TypeDef;
736732

737733
/**
@@ -8395,7 +8391,7 @@ typedef struct
83958391

83968392
/******************* Bit definition for TIM_CCR5 register *******************/
83978393
#define TIM_CCR5_CCR5_Pos (0U)
8398-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
8394+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos)/*!<0x0000FFFF */
83998395
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
84008396
#define TIM_CCR5_GC5C1_Pos (29U)
84018397
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h‎

Lines changed: 12 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -718,21 +718,17 @@ typedef struct
718718

719719
typedef struct
720720
{
721-
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
722-
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
723-
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
724-
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
725-
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
726-
uint16_t RESERVED2; /*!< Reserved, 0x12 */
727-
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
728-
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
729-
uint16_t RESERVED3; /*!< Reserved, 0x1A */
730-
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
731-
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
732-
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
733-
uint16_t RESERVED4; /*!< Reserved, 0x26 */
734-
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
735-
uint16_t RESERVED5; /*!< Reserved, 0x2A */
721+
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
722+
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
723+
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
724+
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
725+
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
726+
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
727+
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
728+
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
729+
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
730+
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
731+
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
736732
} USART_TypeDef;
737733

738734
/**
@@ -8620,7 +8616,7 @@ typedef struct
86208616

86218617
/******************* Bit definition for TIM_CCR5 register *******************/
86228618
#define TIM_CCR5_CCR5_Pos (0U)
8623-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
8619+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos)/*!<0x0000FFFF */
86248620
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
86258621
#define TIM_CCR5_GC5C1_Pos (29U)
86268622
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h‎

Lines changed: 12 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -859,21 +859,17 @@ typedef struct
859859

860860
typedef struct
861861
{
862-
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
863-
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
864-
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
865-
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
866-
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
867-
uint16_t RESERVED2; /*!< Reserved, 0x12 */
868-
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
869-
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
870-
uint16_t RESERVED3; /*!< Reserved, 0x1A */
871-
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
872-
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
873-
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
874-
uint16_t RESERVED4; /*!< Reserved, 0x26 */
875-
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
876-
uint16_t RESERVED5; /*!< Reserved, 0x2A */
862+
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
863+
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
864+
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
865+
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
866+
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
867+
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
868+
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
869+
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
870+
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
871+
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
872+
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
877873
} USART_TypeDef;
878874

879875
/**
@@ -12872,7 +12868,7 @@ typedef struct
1287212868

1287312869
/******************* Bit definition for TIM_CCR5 register *******************/
1287412870
#define TIM_CCR5_CCR5_Pos (0U)
12875-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
12871+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos)/*!<0x0000FFFF */
1287612872
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1287712873
#define TIM_CCR5_GC5C1_Pos (29U)
1287812874
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l432xx.h‎

Lines changed: 12 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -826,21 +826,17 @@ typedef struct
826826

827827
typedef struct
828828
{
829-
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
830-
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
831-
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
832-
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
833-
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
834-
uint16_t RESERVED2; /*!< Reserved, 0x12 */
835-
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
836-
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
837-
uint16_t RESERVED3; /*!< Reserved, 0x1A */
838-
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
839-
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
840-
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
841-
uint16_t RESERVED4; /*!< Reserved, 0x26 */
842-
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
843-
uint16_t RESERVED5; /*!< Reserved, 0x2A */
829+
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
830+
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
831+
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
832+
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
833+
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
834+
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
835+
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
836+
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
837+
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
838+
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
839+
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
844840
} USART_TypeDef;
845841

846842
/**
@@ -12042,7 +12038,7 @@ typedef struct
1204212038

1204312039
/******************* Bit definition for TIM_CCR5 register *******************/
1204412040
#define TIM_CCR5_CCR5_Pos (0U)
12045-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
12041+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos)/*!<0x0000FFFF */
1204612042
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1204712043
#define TIM_CCR5_GC5C1_Pos (29U)
1204812044
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h‎

Lines changed: 12 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -875,21 +875,17 @@ typedef struct
875875

876876
typedef struct
877877
{
878-
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
879-
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
880-
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
881-
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
882-
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
883-
uint16_t RESERVED2; /*!< Reserved, 0x12 */
884-
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
885-
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
886-
uint16_t RESERVED3; /*!< Reserved, 0x1A */
887-
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
888-
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
889-
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
890-
uint16_t RESERVED4; /*!< Reserved, 0x26 */
891-
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
892-
uint16_t RESERVED5; /*!< Reserved, 0x2A */
878+
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
879+
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
880+
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
881+
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
882+
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
883+
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
884+
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
885+
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
886+
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
887+
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
888+
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
893889
} USART_TypeDef;
894890

895891
/**
@@ -13101,7 +13097,7 @@ typedef struct
1310113097

1310213098
/******************* Bit definition for TIM_CCR5 register *******************/
1310313099
#define TIM_CCR5_CCR5_Pos (0U)
13104-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
13100+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos)/*!<0x0000FFFF */
1310513101
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1310613102
#define TIM_CCR5_GC5C1_Pos (29U)
1310713103
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l442xx.h‎

Lines changed: 12 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -827,21 +827,17 @@ typedef struct
827827

828828
typedef struct
829829
{
830-
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
831-
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
832-
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
833-
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
834-
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
835-
uint16_t RESERVED2; /*!< Reserved, 0x12 */
836-
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
837-
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
838-
uint16_t RESERVED3; /*!< Reserved, 0x1A */
839-
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
840-
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
841-
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
842-
uint16_t RESERVED4; /*!< Reserved, 0x26 */
843-
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
844-
uint16_t RESERVED5; /*!< Reserved, 0x2A */
830+
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
831+
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
832+
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
833+
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
834+
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
835+
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
836+
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
837+
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
838+
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
839+
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
840+
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
845841
} USART_TypeDef;
846842

847843
/**
@@ -12267,7 +12263,7 @@ typedef struct
1226712263

1226812264
/******************* Bit definition for TIM_CCR5 register *******************/
1226912265
#define TIM_CCR5_CCR5_Pos (0U)
12270-
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!<0xFFFFFFFF */
12266+
#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos)/*!<0x0000FFFF */
1227112267
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
1227212268
#define TIM_CCR5_GC5C1_Pos (29U)
1227312269
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */

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