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Commit086d1be

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committed
variant: WB: add generic WB5MMGH
Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent329b8bc commit086d1be

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4 files changed

+255
-2
lines changed

4 files changed

+255
-2
lines changed

‎README.md

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Original file line numberDiff line numberDiff line change
@@ -407,6 +407,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
407407
| Status| Device(s)| Name| Release| Notes|
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| :----:| :-------:| ----| :-----:| :----|
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|:green_heart:| STM32WB55CC<br>STM32WB55CE<br>STM32WB55CG| Generic Board|*2.0.0*||
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|:yellow_heart:| STM32WB5MMG| Generic Board|**2.1.0**||
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|:green_heart:| STM32WB55RC<br>STM32WB55RE<br>STM32WB55RG| Generic Board|*2.0.0*||
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###Generic STM32WL boards

‎boards.txt

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@@ -4948,6 +4948,14 @@ GenWB.menu.pnum.GENERIC_WB55CGUX.build.board=GENERIC_WB55CGUX
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GenWB.menu.pnum.GENERIC_WB55CGUX.build.product_line=STM32WB55xx
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GenWB.menu.pnum.GENERIC_WB55CGUX.build.variant=STM32WBxx/WB55C(C-E-G)U
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# Generic WB5MMGHx
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GenWB.menu.pnum.GENERIC_WB5MMGHX=Generic WB5MMGHx
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GenWB.menu.pnum.GENERIC_WB5MMGHX.upload.maximum_size=827392
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GenWB.menu.pnum.GENERIC_WB5MMGHX.upload.maximum_data_size=196608
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GenWB.menu.pnum.GENERIC_WB5MMGHX.build.board=GENERIC_WB5MMGHX
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GenWB.menu.pnum.GENERIC_WB5MMGHX.build.product_line=STM32WB5Mxx
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GenWB.menu.pnum.GENERIC_WB5MMGHX.build.variant=STM32WBxx/WB5MMGH
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# Generic WB55RCVx
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GenWB.menu.pnum.GENERIC_WB55RCVX=Generic WB55RCVx
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GenWB.menu.pnum.GENERIC_WB55RCVX.upload.maximum_size=131072

‎variants/STM32WBxx/WB5MMGH/generic_clock.c

Lines changed: 70 additions & 2 deletions
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@@ -12,6 +12,7 @@
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*/
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#if defined(ARDUINO_GENERIC_WB5MMGHX)
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#include"pins_arduino.h"
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#include"lock_resource.h"
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/**
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* @brief System Clock Configuration
@@ -20,8 +21,75 @@
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*/
2122
WEAKvoidSystemClock_Config(void)
2223
{
23-
/* SystemClock_Config can be generated by STM32CubeMX */
24-
#warning "SystemClock_Config() is empty. Default clock at reset is used."
24+
RCC_OscInitTypeDefRCC_OscInitStruct= {};
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RCC_ClkInitTypeDefRCC_ClkInitStruct= {};
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RCC_PeriphCLKInitTypeDefPeriphClkInitStruct= {};
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/* This prevents concurrent access to RCC registers by CPU2 (M0+) */
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hsem_lock(CFG_HW_RCC_SEMID,HSEM_LOCK_DEFAULT_RETRY);
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/** Configure the main internal regulator output voltage
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*/
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
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hsem_lock(CFG_HW_CLK48_CONFIG_SEMID,HSEM_LOCK_DEFAULT_RETRY);
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
40+
*/
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RCC_OscInitStruct.OscillatorType=RCC_OSCILLATORTYPE_HSI48 |RCC_OSCILLATORTYPE_HSI
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|RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.HSIState=RCC_HSI_ON;
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RCC_OscInitStruct.MSIState=RCC_MSI_ON;
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RCC_OscInitStruct.HSI48State=RCC_HSI48_ON;
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RCC_OscInitStruct.HSICalibrationValue=RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSICalibrationValue=RCC_MSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSIClockRange=RCC_MSIRANGE_6;
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RCC_OscInitStruct.PLL.PLLState=RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource=RCC_PLLSOURCE_MSI;
51+
RCC_OscInitStruct.PLL.PLLM=RCC_PLLM_DIV1;
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RCC_OscInitStruct.PLL.PLLN=32;
53+
RCC_OscInitStruct.PLL.PLLP=RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLR=RCC_PLLR_DIV2;
55+
RCC_OscInitStruct.PLL.PLLQ=RCC_PLLQ_DIV2;
56+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct)!=HAL_OK) {
57+
Error_Handler();
58+
}
59+
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
60+
*/
61+
RCC_ClkInitStruct.ClockType=RCC_CLOCKTYPE_HCLK4 |RCC_CLOCKTYPE_HCLK2
62+
|RCC_CLOCKTYPE_HCLK |RCC_CLOCKTYPE_SYSCLK
63+
|RCC_CLOCKTYPE_PCLK1 |RCC_CLOCKTYPE_PCLK2;
64+
RCC_ClkInitStruct.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK;
65+
RCC_ClkInitStruct.AHBCLKDivider=RCC_SYSCLK_DIV1;
66+
RCC_ClkInitStruct.APB1CLKDivider=RCC_HCLK_DIV1;
67+
RCC_ClkInitStruct.APB2CLKDivider=RCC_HCLK_DIV1;
68+
RCC_ClkInitStruct.AHBCLK2Divider=RCC_SYSCLK_DIV2;
69+
RCC_ClkInitStruct.AHBCLK4Divider=RCC_SYSCLK_DIV1;
70+
71+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct,FLASH_LATENCY_3)!=HAL_OK) {
72+
Error_Handler();
73+
}
74+
/** Initializes the peripherals clocks
75+
*/
76+
PeriphClkInitStruct.PeriphClockSelection=RCC_PERIPHCLK_SMPS |RCC_PERIPHCLK_CLK48SEL
77+
|RCC_PERIPHCLK_USB |RCC_PERIPHCLK_RNG;
78+
PeriphClkInitStruct.UsbClockSelection=RCC_USBCLKSOURCE_HSI48;
79+
PeriphClkInitStruct.RngClockSelection=RCC_RNGCLKSOURCE_HSI48;
80+
PeriphClkInitStruct.SmpsClockSelection=RCC_SMPSCLKSOURCE_HSI;
81+
PeriphClkInitStruct.SmpsDivSelection=RCC_SMPSCLKDIV_RANGE1;
82+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct)!=HAL_OK) {
83+
Error_Handler();
84+
}
85+
LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
86+
LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
87+
LL_PWR_SMPS_Enable();
88+
89+
/* Select HSI as system clock source after Wake Up from Stop mode */
90+
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
91+
92+
hsem_unlock(CFG_HW_RCC_SEMID);
2593
}
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2795
#endif/* ARDUINO_GENERIC_* */
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/*
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******************************************************************************
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**
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** File : LinkerScript.ld
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**
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** Author : STM32CubeIDE
7+
**
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** Abstract : Linker script for STM32WB5MMG Device
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** 1024Kbytes FLASH
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** 256Kbytes RAM
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**
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** Set heap size, stack size and stack location according
13+
** to application requirements.
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**
15+
** Set memory bank area and size if external memory is used.
16+
**
17+
** Target : STMicroelectronics STM32
18+
**
19+
** Distribution: The file is distributed as is without any warranty
20+
** of any kind.
21+
**
22+
*****************************************************************************
23+
** @attention
24+
**
25+
** <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
26+
** All rights reserved.</center></h2>
27+
**
28+
** This software component is licensed by ST under BSD 3-Clause license,
29+
** the "License"; You may not use this file except in compliance with the
30+
** License. You may obtain a copy of theLicense at:
31+
** opensource.org/licenses/BSD-3-Clause
32+
**
33+
*****************************************************************************
34+
*/
35+
36+
/* Entry Point */
37+
ENTRY(Reset_Handler)
38+
39+
/* Highest address of the user mode stack */
40+
_estack = 0x20030000; /* end of RAM */
41+
/* Generate a link error if heap and stack don't fit into RAM */
42+
_Min_Heap_Size = 0x200 ; /* required amount of heap */
43+
_Min_Stack_Size = 0x400 ; /* required amount of stack */
44+
45+
/* Specify the memory areas */
46+
MEMORY
47+
{
48+
FLASH (rx) :ORIGIN = 0x08000000 + LD_FLASH_OFFSET,LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
49+
RAM1 (xrw) :ORIGIN = 0x20000004,LENGTH = LD_MAX_DATA_SIZE - 4
50+
RAM_SHARED (xrw) :ORIGIN = 0x20030000,LENGTH = 10K
51+
}
52+
53+
/* Define output sections */
54+
SECTIONS
55+
{
56+
/* The startup code goes first into FLASH */
57+
.isr_vector :
58+
{
59+
. =ALIGN(4);
60+
KEEP(*(.isr_vector)) /* Startup code */
61+
. =ALIGN(4);
62+
} >FLASH
63+
64+
/* The program code and other data goes into FLASH */
65+
.text :
66+
{
67+
. =ALIGN(4);
68+
*(.text) /* .text sections (code) */
69+
*(.text*) /* .text* sections (code) */
70+
*(.glue_7) /* glue arm to thumb code */
71+
*(.glue_7t) /* glue thumb to arm code */
72+
*(.eh_frame)
73+
74+
KEEP (*(.init))
75+
KEEP (*(.fini))
76+
77+
. =ALIGN(4);
78+
_etext = .; /* define a global symbols at end of code */
79+
} >FLASH
80+
81+
/* Constant data goes into FLASH */
82+
.rodata :
83+
{
84+
. =ALIGN(4);
85+
*(.rodata) /* .rodata sections (constants, strings, etc.) */
86+
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
87+
. =ALIGN(4);
88+
} >FLASH
89+
90+
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
91+
.ARM : {
92+
__exidx_start = .;
93+
*(.ARM.exidx*)
94+
__exidx_end = .;
95+
} >FLASH
96+
97+
.preinit_array :
98+
{
99+
PROVIDE_HIDDEN (__preinit_array_start = .);
100+
KEEP (*(.preinit_array*))
101+
PROVIDE_HIDDEN (__preinit_array_end = .);
102+
} >FLASH
103+
.init_array :
104+
{
105+
PROVIDE_HIDDEN (__init_array_start = .);
106+
KEEP (*(SORT(.init_array.*)))
107+
KEEP (*(.init_array*))
108+
PROVIDE_HIDDEN (__init_array_end = .);
109+
} >FLASH
110+
.fini_array :
111+
{
112+
PROVIDE_HIDDEN (__fini_array_start = .);
113+
KEEP (*(SORT(.fini_array.*)))
114+
KEEP (*(.fini_array*))
115+
PROVIDE_HIDDEN (__fini_array_end = .);
116+
} >FLASH
117+
118+
/* used by the startup to initialize data */
119+
_sidata =LOADADDR(.data);
120+
121+
/* Initialized data sections goes into RAM, load LMA copy after code */
122+
.data :
123+
{
124+
. =ALIGN(4);
125+
_sdata = .; /* create a global symbol at data start */
126+
*(.data) /* .data sections */
127+
*(.data*) /* .data* sections */
128+
*(.RamFunc) /* .RamFunc sections */
129+
*(.RamFunc*) /* .RamFunc* sections */
130+
131+
. =ALIGN(4);
132+
_edata = .; /* define a global symbol at data end */
133+
} >RAM1 AT> FLASH
134+
135+
/* Uninitialized data section */
136+
. =ALIGN(4);
137+
.bss :
138+
{
139+
/* This is used by the startup in order to initialize the .bss secion */
140+
_sbss = .; /* define a global symbol at bss start */
141+
__bss_start__ = _sbss;
142+
*(.bss)
143+
*(.bss*)
144+
*(COMMON)
145+
146+
. =ALIGN(4);
147+
_ebss = .; /* define a global symbol at bss end */
148+
__bss_end__ = _ebss;
149+
} >RAM1
150+
151+
/* User_heap_stack section, used to check that there is enough RAM left */
152+
._user_heap_stack :
153+
{
154+
. =ALIGN(8);
155+
PROVIDE ( end = . );
156+
PROVIDE ( _end = . );
157+
. = . + _Min_Heap_Size;
158+
. = . + _Min_Stack_Size;
159+
. =ALIGN(8);
160+
} >RAM1
161+
162+
/* Remove information from the standard libraries */
163+
/DISCARD/ :
164+
{
165+
libc.a ( * )
166+
libm.a ( * )
167+
libgcc.a ( * )
168+
}
169+
170+
.ARM.attributes 0 : { *(.ARM.attributes) }
171+
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
172+
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
173+
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
174+
}
175+
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