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Commit02f4516

Browse files
committed
system(F3) update STM32F3xx HAL Drivers to v1.5.8
Included in STM32CubeF3 FW v1.11.5Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent4782f07 commit02f4516

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73 files changed

+1991
-1368
lines changed

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73 files changed

+1991
-1368
lines changed

‎system/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h‎

Lines changed: 54 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
******************************************************************************
88
* @attention
99
*
10-
* Copyright (c)2023 STMicroelectronics.
10+
* Copyright (c)2021 STMicroelectronics.
1111
* All rights reserved.
1212
*
1313
* This software is licensed under terms that can be found in the LICENSE file
@@ -37,16 +37,12 @@ extern "C" {
3737
#defineAES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
3838
#defineAES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
3939
#defineAES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
40-
#if defined(STM32U5)|| defined(STM32H7)|| defined(STM32MP1)
40+
#if defined(STM32H7)|| defined(STM32MP1)
4141
#defineCRYP_DATATYPE_32B CRYP_NO_SWAP
4242
#defineCRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
4343
#defineCRYP_DATATYPE_8B CRYP_BYTE_SWAP
4444
#defineCRYP_DATATYPE_1B CRYP_BIT_SWAP
45-
#if defined(STM32U5)
46-
#defineCRYP_CCF_CLEAR CRYP_CLEAR_CCF
47-
#defineCRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
48-
#endif/* STM32U5 */
49-
#endif/* STM32U5 || STM32H7 || STM32MP1 */
45+
#endif/* STM32H7 || STM32MP1 */
5046
/**
5147
* @}
5248
*/
@@ -279,7 +275,7 @@ extern "C" {
279275
#defineDAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
280276
#defineDAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
281277

282-
#if defined(STM32G4)|| defined(STM32L5)|| defined(STM32H7)|| defined (STM32U5)
278+
#if defined(STM32G4)|| defined(STM32H7)|| defined (STM32U5)
283279
#defineDAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
284280
#defineDAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
285281
#endif
@@ -552,6 +548,16 @@ extern "C" {
552548
#defineOB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
553549
#defineOB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
554550
#endif/* STM32U5 */
551+
#if defined(STM32U0)
552+
#defineOB_USER_nRST_STOP OB_USER_NRST_STOP
553+
#defineOB_USER_nRST_STDBY OB_USER_NRST_STDBY
554+
#defineOB_USER_nRST_SHDW OB_USER_NRST_SHDW
555+
#defineOB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
556+
#defineOB_USER_nBOOT0 OB_USER_NBOOT0
557+
#defineOB_USER_nBOOT1 OB_USER_NBOOT1
558+
#defineOB_nBOOT0_RESET OB_NBOOT0_RESET
559+
#defineOB_nBOOT0_SET OB_NBOOT0_SET
560+
#endif/* STM32U0 */
555561

556562
/**
557563
* @}
@@ -1243,10 +1249,10 @@ extern "C" {
12431249
#defineRTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
12441250
#defineRTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
12451251

1246-
#if defined(STM32H5)
1252+
#if defined(STM32H5)|| defined(STM32H7RS)
12471253
#defineTAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
12481254
#defineTAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
1249-
#endif/* STM32H5 */
1255+
#endif/* STM32H5|| STM32H7RS*/
12501256

12511257
#if defined(STM32WBA)
12521258
#defineTAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1258,10 +1264,10 @@ extern "C" {
12581264
#defineTAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
12591265
#endif/* STM32WBA */
12601266

1261-
#if defined(STM32H5)|| defined(STM32WBA)
1267+
#if defined(STM32H5)|| defined(STM32WBA)|| defined(STM32H7RS)
12621268
#defineTAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
12631269
#defineTAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
1264-
#endif/* STM32H5 || STM32WBA */
1270+
#endif/* STM32H5 || STM32WBA|| STM32H7RS*/
12651271

12661272
#if defined(STM32F7)
12671273
#defineRTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -1599,6 +1605,8 @@ extern "C" {
15991605
#defineETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U/* MAC small FIFO read / write controllers active */
16001606
#defineETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U/* MAC MII receive protocol engine active */
16011607

1608+
#defineETH_TxPacketConfig ETH_TxPacketConfigTypeDef/* Transmit Packet Configuration structure definition */
1609+
16021610
/**
16031611
* @}
16041612
*/
@@ -1991,12 +1999,12 @@ extern "C" {
19911999
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
19922000
* @{
19932001
*/
1994-
#if defined(STM32H5)|| defined(STM32WBA)
2002+
#if defined(STM32H5)|| defined(STM32WBA)|| defined(STM32H7RS)
19952003
#defineHAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
19962004
#defineHAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
19972005
#defineHAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
19982006
#defineHAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
1999-
#endif/* STM32H5 || STM32WBA */
2007+
#endif/* STM32H5 || STM32WBA|| STM32H7RS*/
20002008

20012009
/**
20022010
* @}
@@ -2311,8 +2319,8 @@ extern "C" {
23112319
#define__HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
23122320
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
23132321
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
2314-
#endif
2315-
#if defined(STM32F302xE)|| defined(STM32F302xC)
2322+
#endif
2323+
#if defined(STM32F302xE)|| defined(STM32F302xC)
23162324
#define__HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
23172325
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
23182326
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2345,8 +2353,8 @@ extern "C" {
23452353
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
23462354
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
23472355
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
2348-
#endif
2349-
#if defined(STM32F303xE)|| defined(STM32F398xx)|| defined(STM32F303xC)|| defined(STM32F358xx)
2356+
#endif
2357+
#if defined(STM32F303xE)|| defined(STM32F398xx)|| defined(STM32F303xC)|| defined(STM32F358xx)
23502358
#define__HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
23512359
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
23522360
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2403,8 +2411,8 @@ extern "C" {
24032411
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
24042412
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
24052413
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
2406-
#endif
2407-
#if defined(STM32F373xC)||defined(STM32F378xx)
2414+
#endif
2415+
#if defined(STM32F373xC)||defined(STM32F378xx)
24082416
#define__HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
24092417
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
24102418
#define__HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2421,7 +2429,7 @@ extern "C" {
24212429
__HAL_COMP_COMP2_EXTI_GET_FLAG())
24222430
#define__HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
24232431
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
2424-
#endif
2432+
#endif
24252433
#else
24262434
#define__HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
24272435
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2723,6 +2731,12 @@ extern "C" {
27232731
#define__APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
27242732
#define__APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
27252733
#define__APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
2734+
#if defined(STM32C0)
2735+
#define__HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
2736+
#define__HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
2737+
#define__HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
2738+
#define__HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
2739+
#endif/* STM32C0 */
27262740
#define__BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
27272741
#define__BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
27282742
#define__BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3646,8 +3660,12 @@ extern "C" {
36463660
#defineRCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
36473661
#defineRCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
36483662

3663+
#if defined(STM32U0)
3664+
#defineRCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
3665+
#endif
3666+
36493667
#if defined(STM32L4)|| defined(STM32WB)|| defined(STM32G0)|| defined(STM32G4)|| defined(STM32L5)|| \
3650-
defined(STM32WL)|| defined(STM32C0)
3668+
defined(STM32WL)|| defined(STM32C0)|| defined(STM32H7RS)|| defined(STM32U0)
36513669
#defineRCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
36523670
#else
36533671
#defineRCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3749,8 +3767,10 @@ extern "C" {
37493767
#define__HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
37503768
#defineRCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
37513769
#defineRCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
3770+
#if !defined(STM32U0)
37523771
#defineRCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
37533772
#defineRCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
3773+
#endif
37543774

37553775
#defineRCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
37563776
#defineRCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3896,7 +3916,8 @@ extern "C" {
38963916
*/
38973917
#if defined (STM32G0)|| defined (STM32L5)|| defined (STM32L412xx)|| defined (STM32L422xx)|| \
38983918
defined (STM32L4P5xx)|| defined (STM32L4Q5xx)|| defined (STM32G4)|| defined (STM32WL)|| defined (STM32U5)|| \
3899-
defined (STM32WBA)|| defined (STM32H5)|| defined (STM32C0)
3919+
defined (STM32WBA)|| defined (STM32H5)|| \
3920+
defined (STM32C0)|| defined (STM32H7RS)|| defined (STM32U0)
39003921
#else
39013922
#define__HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39023923
#endif
@@ -3931,6 +3952,13 @@ extern "C" {
39313952
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
39323953
#endif/* STM32F1 */
39333954

3955+
#if defined (STM32F0)|| defined (STM32F2)|| defined (STM32F3)|| defined (STM32F4)|| defined (STM32F7)|| \
3956+
defined (STM32H7)|| \
3957+
defined (STM32L0)|| defined (STM32L1)|| \
3958+
defined (STM32WB)
3959+
#define__HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
3960+
#endif
3961+
39343962
#defineIS_ALARM IS_RTC_ALARM
39353963
#defineIS_ALARM_MASK IS_RTC_ALARM_MASK
39363964
#defineIS_TAMPER IS_RTC_TAMPER
@@ -4212,6 +4240,9 @@ extern "C" {
42124240
#define__HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
42134241

42144242
#defineTIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
4243+
4244+
#defineTIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
4245+
#defineTIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
42154246
/**
42164247
* @}
42174248
*/

‎system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,11 @@ typedef struct
204204
/**
205205
* @brief CAN handle Structure definition
206206
*/
207+
#ifUSE_HAL_CAN_REGISTER_CALLBACKS==1
207208
typedefstruct__CAN_HandleTypeDef
209+
#else
210+
typedefstruct
211+
#endif/* USE_HAL_CAN_REGISTER_CALLBACKS */
208212
{
209213
CAN_TypeDef*Instance;/*!< Register base address */
210214

‎system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -271,6 +271,8 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
271271
*/
272272
/* Peripheral Control functions ***********************************************/
273273
#if (__MPU_PRESENT==1U)
274+
voidHAL_MPU_EnableRegion(uint32_tRegionNumber);
275+
voidHAL_MPU_DisableRegion(uint32_tRegionNumber);
274276
voidHAL_MPU_ConfigRegion(MPU_Region_InitTypeDef*MPU_Init);
275277
#endif/* __MPU_PRESENT */
276278
uint32_tHAL_NVIC_GetPriorityGrouping(void);

‎system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_crc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -318,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
318318
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
319319
* @{
320320
*/
321-
HAL_CRC_StateTypeDefHAL_CRC_GetState(CRC_HandleTypeDef*hcrc);
321+
HAL_CRC_StateTypeDefHAL_CRC_GetState(constCRC_HandleTypeDef*hcrc);
322322
/**
323323
* @}
324324
*/

‎system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -118,8 +118,6 @@ typedef enum
118118
HAL_I2C_STATE_BUSY_RX_LISTEN=0x2AU,/*!< Address Listen Mode and Data Reception
119119
process is ongoing */
120120
HAL_I2C_STATE_ABORT=0x60U,/*!< Abort user request ongoing */
121-
HAL_I2C_STATE_TIMEOUT=0xA0U,/*!< Timeout state */
122-
HAL_I2C_STATE_ERROR=0xE0U/*!< Error */
123121

124122
}HAL_I2C_StateTypeDef;
125123

‎system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,10 +24,10 @@
2424
extern"C" {
2525
#endif
2626

27+
#if defined(FMC_BANK3)
2728

2829
/* Includes ------------------------------------------------------------------*/
2930
#include"stm32f3xx_ll_fmc.h"
30-
#if defined(FMC_BANK3)
3131

3232
/** @addtogroup STM32F3xx_HAL_Driver
3333
* @{
@@ -105,7 +105,6 @@ typedef struct
105105
FunctionalStateExtraCommandEnable;/*!< NAND extra command needed for Page reading mode. This
106106
parameter is mandatory for some NAND parts after the read
107107
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
108-
Example: Toshiba THTH58BYG3S0HBAI6.
109108
This parameter could be ENABLE or DISABLE
110109
Please check the Read Mode sequence in the NAND device datasheet */
111110
}NAND_DeviceConfigTypeDef;

‎system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,10 +24,10 @@
2424
extern"C" {
2525
#endif
2626

27+
#if defined(FMC_BANK1)
2728

2829
/* Includes ------------------------------------------------------------------*/
2930
#include"stm32f3xx_ll_fmc.h"
30-
#if defined(FMC_BANK1)
3131

3232
/** @addtogroup STM32F3xx_HAL_Driver
3333
* @{
@@ -184,7 +184,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
184184
HAL_StatusTypeDefHAL_NOR_DeInit(NOR_HandleTypeDef*hnor);
185185
voidHAL_NOR_MspInit(NOR_HandleTypeDef*hnor);
186186
voidHAL_NOR_MspDeInit(NOR_HandleTypeDef*hnor);
187-
voidHAL_NOR_MspWait(constNOR_HandleTypeDef*hnor,uint32_tTimeout);
187+
voidHAL_NOR_MspWait(NOR_HandleTypeDef*hnor,uint32_tTimeout);
188188
/**
189189
* @}
190190
*/
@@ -235,7 +235,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
235235

236236
/* NOR State functions ********************************************************/
237237
HAL_NOR_StateTypeDefHAL_NOR_GetState(constNOR_HandleTypeDef*hnor);
238-
HAL_NOR_StatusTypeDefHAL_NOR_GetStatus(constNOR_HandleTypeDef*hnor,uint32_tAddress,uint32_tTimeout);
238+
HAL_NOR_StatusTypeDefHAL_NOR_GetStatus(NOR_HandleTypeDef*hnor,uint32_tAddress,uint32_tTimeout);
239239
/**
240240
* @}
241241
*/

‎system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h‎

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -334,7 +334,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
334334
HAL_StatusTypeDefHAL_PCD_EP_Abort(PCD_HandleTypeDef*hpcd,uint8_tep_addr);
335335
HAL_StatusTypeDefHAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef*hpcd);
336336
HAL_StatusTypeDefHAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef*hpcd);
337-
uint32_tHAL_PCD_EP_GetRxCount(PCD_HandleTypeDef*hpcd,uint8_tep_addr);
337+
uint32_tHAL_PCD_EP_GetRxCount(PCD_HandleTypeDefconst*hpcd,uint8_tep_addr);
338338
/**
339339
* @}
340340
*/
@@ -343,7 +343,7 @@ uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr
343343
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
344344
* @{
345345
*/
346-
PCD_StateTypeDefHAL_PCD_GetState(PCD_HandleTypeDef*hpcd);
346+
PCD_StateTypeDefHAL_PCD_GetState(PCD_HandleTypeDefconst*hpcd);
347347
/**
348348
* @}
349349
*/
@@ -801,20 +801,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
801801
\
802802
*(pdwReg) &= 0x3FFU; \
803803
\
804-
if ((wCount)> 62U) \
804+
if ((wCount)== 0U) \
805805
{ \
806-
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
806+
*(pdwReg) |= USB_CNTRX_BLSIZE; \
807+
} \
808+
else if ((wCount) <= 62U) \
809+
{ \
810+
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
807811
} \
808812
else \
809813
{ \
810-
if ((wCount) == 0U) \
811-
{ \
812-
*(pdwReg) |= USB_CNTRX_BLSIZE; \
813-
} \
814-
else \
815-
{ \
816-
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
817-
} \
814+
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
818815
} \
819816
} while(0)/* PCD_SET_EP_CNT_RX_REG */
820817

‎system/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rtc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -795,7 +795,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
795795

796796
#defineRTC_TIMEOUT_VALUE 1000U
797797

798-
#defineRTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17/*!< External interrupt line 17Connected to the RTC Alarm event */
798+
#defineRTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17/*!< External interrupt line 17connected to the RTC Alarm event */
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/**
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* @}
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*/

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