|
1 | 1 | # Common fields between v2 A, B and C peripherals |
2 | 2 |
|
3 | | -CR1: |
4 | | -DEAT:[0, 0b11111] |
5 | | -DEDT:[0, 0b11111] |
6 | | -CMIE: |
7 | | -Disabled:[0, Interrupt is disabled] |
8 | | -Enabled:[1, Interrupt is generated when the CMF bit is set in the ISR register] |
9 | | -MME: |
10 | | -Disabled:[0, Receiver in active mode permanently] |
11 | | -Enabled:[1, Receiver can switch between mute mode and active mode] |
12 | | -WAKE: |
13 | | -Idle:[0, Idle line] |
14 | | -Address:[1, Address mask] |
15 | | -PCE: |
16 | | -Disabled:[0, Parity control disabled] |
17 | | -Enabled:[1, Parity control enabled] |
18 | | -PS: |
19 | | -Even:[0, Even parity] |
20 | | -Odd:[1, Odd parity] |
21 | | -PEIE: |
22 | | -Disabled:[0, Interrupt is disabled] |
23 | | -Enabled:[1, "Interrupt is generated whenever PE=1 in the ISR register"] |
24 | | -TXEIE: |
25 | | -Disabled:[0, Interrupt is disabled] |
26 | | -Enabled:[1, "Interrupt is generated whenever TXE=1 in the ISR register"] |
27 | | -TCIE: |
28 | | -Disabled:[0, Interrupt is disabled] |
29 | | -Enabled:[1, "Interrupt is generated whenever TC=1 in the ISR register"] |
30 | | -RXNEIE: |
31 | | -Disabled:[0, Interrupt is disabled] |
32 | | -Enabled:[1, "Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register"] |
33 | | -IDLEIE: |
34 | | -Disabled:[0, Interrupt is disabled] |
35 | | -Enabled:[1, "Interrupt is generated whenever IDLE=1 in the ISR register"] |
36 | | -TE: |
37 | | -Disabled:[0, Transmitter is disabled] |
38 | | -Enabled:[1, Transmitter is enabled] |
39 | | -RE: |
40 | | -Disabled:[0, Receiver is disabled] |
41 | | -Enabled:[1, Receiver is enabled] |
42 | | -UE: |
43 | | -Disabled:[0, UART is disabled] |
44 | | -Enabled:[1, UART is enabled] |
| 3 | +_include:uart_common.yaml |
| 4 | + |
45 | 5 | CR2: |
46 | | -ADD:[0, 0xFF] |
47 | | -MSBFIRST: |
48 | | -LSB:[0, "data is transmitted/received with data bit 0 first, following the start bit"] |
49 | | -MSB:[1, "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"] |
50 | | -TXINV: |
51 | | -Standard:[0, TX pin signal works using the standard logic levels] |
52 | | -Inverted:[1, TX pin signal values are inverted] |
53 | | -RXINV: |
54 | | -Standard:[0, RX pin signal works using the standard logic levels] |
55 | | -Inverted:[1, RX pin signal values are inverted] |
56 | | -DATAINV: |
57 | | -Positive:[0, Logical data from the data register are send/received in positive/direct logic] |
58 | | -Negative:[1, Logical data from the data register are send/received in negative/inverse logic] |
59 | | -SWAP: |
60 | | -Standard:[0, TX/RX pins are used as defined in standard pinout] |
61 | | -Swapped:[1, The TX and RX pins functions are swapped] |
62 | 6 | STOP: |
63 | 7 | Stop1:[0, 1 stop bit] |
64 | 8 | Stop0p5:[1, 0.5 stop bit] |
|
67 | 11 | "?~CLKEN": |
68 | 12 | Disabled:[0, CK pin disabled] |
69 | 13 | Enabled:[1, CK pin enabled] |
70 | | -ADDM7: |
71 | | -Bit4:[0, 4-bit address detection] |
72 | | -Bit7:[1, 7-bit address detection] |
73 | | -CR3: |
74 | | -DEP: |
75 | | -High:[0, DE signal is active high] |
76 | | -Low:[1, DE signal is active low] |
77 | | -DEM: |
78 | | -Disabled:[0, DE function is disabled] |
79 | | -Enabled:[1, The DE signal is output on the RTS pin] |
80 | | -DDRE: |
81 | | -NotDisabled:[0, DMA is not disabled in case of reception error] |
82 | | -Disabled:[1, DMA is disabled following a reception error] |
83 | | -OVRDIS: |
84 | | -Enabled:[0, "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"] |
85 | | -Disabled: |
86 | | -[ |
87 | | -1, |
88 | | -Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register, |
89 | | -] |
90 | | -CTSIE: |
91 | | -Disabled:[0, Interrupt is inhibited] |
92 | | -Enabled:[1, "An interrupt is generated whenever CTSIF=1 in the ISR register"] |
93 | | -CTSE: |
94 | | -Disabled:[0, CTS hardware flow control disabled] |
95 | | -Enabled:[1, "CTS mode enabled, data is only transmitted when the CTS input is asserted"] |
96 | | -RTSE: |
97 | | -Disabled:[0, RTS hardware flow control disabled] |
98 | | -Enabled:[1, "RTS output enabled, data is only requested when there is space in the receive buffer"] |
99 | | -DMAT: |
100 | | -Disabled:[0, DMA mode is disabled for transmission] |
101 | | -Enabled:[1, DMA mode is enabled for transmission] |
102 | | -DMAR: |
103 | | -Disabled:[0, DMA mode is disabled for reception] |
104 | | -Enabled:[1, DMA mode is enabled for reception] |
105 | | -HDSEL: |
106 | | -NotSelected:[0, Half duplex mode is not selected] |
107 | | -Selected:[1, Half duplex mode is selected] |
108 | | -EIE: |
109 | | -Disabled:[0, Interrupt is inhibited] |
110 | | -Enabled:[1, "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"] |
111 | | -RQR: |
112 | | -RXFRQ: |
113 | | -Discard: |
114 | | -[ |
115 | | -1, |
116 | | -"clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition", |
117 | | -] |
118 | | -MMRQ: |
119 | | -Mute:[1, Puts the USART in mute mode and sets the RWU flag] |
120 | | -SBKRQ: |
121 | | -Break: |
122 | | -[1, "sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"] |
123 | | -ISR: |
124 | | -PE: |
125 | | -NoError:[0, No parity error] |
126 | | -Error:[1, Parity error] |
127 | | -FE: |
128 | | -NoError:[0, No Framing error is detected] |
129 | | -Error:[1, Framing error or break character is detected] |
130 | | -"NE,NF": |
131 | | -NoNoise:[0, No noise is detected] |
132 | | -Noise:[1, Noise is detected] |
133 | | -ORE: |
134 | | -NoOverrun:[0, No Overrun error] |
135 | | -Overrun:[1, Overrun error is detected] |
136 | | -IDLE: |
137 | | -NoIdle:[0, No Idle Line is detected] |
138 | | -Idle:[1, Idle Line is detected] |
139 | | -"RXNE,RXFNE": |
140 | | -NoData:[0, Data is not received] |
141 | | -DataReady:[1, Received data is ready to be read] |
142 | | -TC: |
143 | | -TxNotComplete:[0, Transmission is not complete] |
144 | | -TxComplete:[1, Transmission is complete] |
145 | | -"TXE,TXFNF": |
146 | | -Full:[0, Transmit FIFO is full] |
147 | | -NotFull:[1, Transmit FIFO is not full] |
148 | | -CTSIF: |
149 | | -NotChanged:[0, No change occurred on the CTS status line] |
150 | | -Changed:[1, A change occurred on the CTS status line] |
151 | | -CTS: |
152 | | -Set:[0, CTS line set] |
153 | | -Reset:[1, CTS line reset] |
154 | | -BUSY: |
155 | | -Idle:[0, USART is idle (no reception)] |
156 | | -Busy:[1, Reception on going] |
157 | | -CMF: |
158 | | -NoMatch:[0, No Character match detected] |
159 | | -Match:[1, Character match detected] |
160 | | -SBKF: |
161 | | -NoBreak:[0, No break character transmitted] |
162 | | -Break:[1, Break character transmitted] |
163 | | -TEACK: |
164 | | -ICR: |
165 | | -"*": |
166 | | -_W1C:{} |
167 | | -CMCF: |
168 | | -Clear:[1, Clears the CMF flag in the ISR register] |
169 | | -CTSCF: |
170 | | -Clear:[1, Clears the CTSIF flag in the ISR register] |
171 | | -TCCF: |
172 | | -Clear:[1, Clears the TC flag in the ISR register] |
173 | | -IDLECF: |
174 | | -Clear:[1, Clears the IDLE flag in the ISR register] |
175 | | -ORECF: |
176 | | -Clear:[1, Clears the ORE flag in the ISR register] |
177 | | -"NCF,NCEF,NECF": |
178 | | -Clear:[1, Clears the NF flag in the ISR register] |
179 | | -FECF: |
180 | | -Clear:[1, Clears the FE flag in the ISR register] |
181 | | -PECF: |
182 | | -Clear:[1, Clears the PE flag in the ISR register] |
183 | | -RDR: |
184 | | -RDR:[0, 0x1FF] |
185 | | -TDR: |
186 | | -TDR:[0, 0x1FF] |