Become a sponsor toJakub Cabal
Hello everyone. 👋
My name is Jakub Cabal and I am an FPGA engineer 👨💻 and creator of several open-source RTL projects including those listed below. In my work, I mainly focus on the processing of network traffic 🌐 on FPGAs and I also have experience with several communication interfaces, including Ethernet and PCIe.
- rmii-firewall-fpga = The RMII Firewall FPGA allows to filter Ethernet packets.
- spi-fpga = The SPI master and SPI slave are simple controllers FPGAs.
- uart-for-fpga = The simple UART for FPGA is UART controller for serial communication.
Your support will help me further develop interesting open-source projects built on FPGA or create new useful open-source RTL IP cores. Your ideas 💡 are also welcome.
Thank you for your support! 💙
Featured work
- jakubcabal/uart-for-fpga
Simple UART controller for FPGA written in VHDL
VHDL 95 - jakubcabal/spi-fpga
SPI master and SPI slave for FPGA written in VHDL
VHDL 170 - jakubcabal/pipemania-fpga-game
Pipe Mania - Game for FPGA written in VHDL
VHDL 9 - jakubcabal/rmii-firewall-fpga
RMII Firewall FPGA
VHDL 22 - jakubcabal/sdram-tester-fpga
SDRAM Tester implemented in FPGA
VHDL 10 - jakubcabal/cyc1000-rsu
The CYC1000 FPGA Remote System Upgrade project
VHDL 7