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PDN-0185 Insufficient width to add straps on layer#3539

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philiprbrenan asked this question inHelp (Q&A)
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When compiling:

module find_verilog(stop, clock);          input                     clock;         output                    stop;          integer  step;                           always @ (posedge clock) begin                step <= 1;  end // Alwaysendmodule

With:

#!/usr/bin/env python3from siliconcompiler import Chip                                  from siliconcompiler.targets import freepdk45_demoif __name__ == "__main__":    chip = Chip('find_verilog')                                       chip.input('find_verilog.v')                                      chip.set('design', 'find_verilog')                                chip.use(freepdk45_demo)                                          chip.set('option', 'remote', False)                               chip.set('option', 'nodisplay', True)                             chip.set('option', 'loglevel', 'warning')                         chip.set('option', 'clean', True)                                 chip.run()                                                        chip.summary()    chip.snapshot()

I get:

| ERROR   | job0 | floorplan.power_grid | 0 | 215: [ERROR PDN-0185] Insufficient width (1.52 um) to add straps on layer metal4 in grid "grid" with total strap width 1.2 um and offset 2.0 um

Plese tell me how I can overcome this problem?

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Replies: 4 comments 2 replies

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The error stems from the power grid definitions, which has some ability to adapt, but in this case, the circuit it likely too small to be (or has no logic generated). You can specify a floorplan withcontraint,outline to increase the size of the block

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The following minimal design does work as long as the following constraints are
set otherwise theERROR PDN-0185 Insufficient width to add straps message
occurs.

    chip.set('constraint', 'outline', [(0, 0), (4, 4)])    chip.set('constraint', 'density', 8)

In particular it is sensitive to density: a density of9 fails whereas8 succeeds.

Might it be worth automating the application of these constraints to avoid the inevitable
confusion that has occurred and will continue to occur when new users try to synthesize
a basic design?

As things stand, might not new users think they will always have to provide the outline
and density as they grow their design because they will not know, other than through
occasional experimentation, whether Silicon Compiler can perform this important task
for them?

Minimal design:

module find_verilog(in, out, clock);                                               input                     in;                                                    input                     clock;                                              output reg                out;                                                                                                                             always @ (posedge clock) begin                             out <= in;  end endmodule

Compiled successfully with:

#!/usr/bin/env python3from siliconcompiler import Chip                                 from siliconcompiler.targets import freepdk45_demoif __name__ == "__main__":    chip = Chip('find_verilog')                                               chip.input('find_verilog.v')                                              chip.set('design', 'find_verilog')                                      chip.use(freepdk45_demo)                                             chip.clock('clock', period=1)                                            chip.set('option', 'remote', False)                                   chip.set('option', 'nodisplay', True)                                chip.set('option', 'loglevel', 'warning')                           chip.set('option', 'clean', True)                                        chip.set('constraint', 'outline', [(0, 0), (4, 4)])    chip.set('constraint', 'density', 8)    chip.run()                                                                     chip.summary()    chip.snapshot()
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1 reply
@gadfort
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@philiprbrenan The issue here is that the design is so trivial as to cause issues. The powergrid scripts are the culprit here, they expect a minimum size, so that is something we could consider fixing over in lambdapdk (which is where the power grid scripts reside).

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Conversely, this does work without the outline and density constraints:

module find_verilog(in, out, clock);             input        [7:0]              in;            input                         clock;           output reg   [7:0]             out;                                                           always @ (posedge clock) begin                      out <= in;  end // Alwaysendmodule

Specifying 4 bits as the input width does require the outline and density constraints to compile successfully.

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0 replies
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Once the GDS is generated with this minimal design, how to create a padring? Any specific help would be highly appreciated.

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1 reply
@aolofsson
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please open a separate issue for this

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