Eventually we will want to be able to make use of simd operations for f16 and f128, now that we have primitives to represent them. Possibilities that I know of:

• Aarch64 neon supportsfloat16x{4,8}https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:@navigationhierarchiessimdisa=[Neon]&f:@navigationhierarchiesreturnbasetype=[float]&f:@navigationhierarchieselementbitsize=[16]&q=.
  • Implementation:AArch64: Add NEON fp16 intrinsics stdarch#1726
  • Tracking issue:Tracking Issue for NEON fp16 intrinsics #136306
• Arm sve supportsfloat16x{1,2}https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:@navigationhierarchiesreturnbasetype=[float]&f:@navigationhierarchieselementbitsize=[16]&f:@navigationhierarchiessimdisa=[sve2,sve]&q=
  • We probably can't support this until our runtime-sized types story is better
• RISC-V apparently has both f16 and f128https://five-embeddev.com/riscv-user-isa-manual/riscv-user-2.2/v.html
  • Similarly relies on the "V" extension which has runtime-sized typesTracking Issue for RISC-V Ratified Extensions Intrinsics #114544
• NVIDIA PTX has f16 SIMD
  • Implementation:NVPTX: Add f16 SIMD intrinsics stdarch#1626
  • SubmoduleUpdate stdarch submodule #128866
  • Tracking issue:Tracking Issue for NVPTX arch intrinsics #111199
• x86 with +avx512fp16
  • Implementation:Implement AVX512_FP16 stdarch#1605
  • Submodule:Update the stdarch submodule #128466
  • Tracking issue:Tracking Issue for AVX512_FP16 intrinsics #127213
• Portable SIMD should eventually be able to support these operations

Probably some work/research overlap with adding assembly#125398

Tracking issue:#116909