f16 should be okay to pass in GPRs.f16 andf128 can likely get passed in vector or FP registers, but we should prefer to only allow this if an ABI is specified for the type.

Loose list of platforms that specify an ABI:

• arm-*,armv7-*,aarch64-*,https://developer.arm.com/documentation/den0024/a/Porting-to-A64/Data-types
  • Addf16 inline ASM support for 32-bit ARM #126555
  • Enable f16 in assembly on aarch64 platforms that support it #127043
• PowerPC PowerISA apparently has a half-precision format according to section 7.3.2.1https://files.openpower.foundation/s/dAYSdGzTfW4j2r2, but I can't get LLVM to emit any instructions for it. Per others, the VSX feature on PowerISA 3.1+ has conversion support forf16, and the SVP64 feature (which I can't find documented anywhere) adds full hardware support
• MIPS with the MSA extension...?https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00868-1D-MSA64-AFP-01.12.pdf section 3.1 says "16-bit floating-point storage format is supported through conversion instructions to/from 32-bit floating-point data.", I am unsure whether its vector registers have any special support
• riscv64gc with the Q extension:https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2023-05-23/src/q-st-ext.adoc
  • Addf16 inline ASM support for RISC-V #126530
• x86 specifies an ABI for these types, and AVX512fp16 can use them
  • Addf16 andf128 inline ASM support forx86 andx86-64 #126417

Additionally, forf128:

• s390x supportsf128, referred to as "BFP Extended Format" inhttps://publibfp.dhe.ibm.com/epubs/pdf/a227832c.pdf. I am not sure if this comes with any special instructions.
• PowerPC with-Ctarget-cpu=pwr9 seems to have f128 support via instructions likexsaddqp

Tracking issue:#116909