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Provide an efficient and flexible register model for the Hardware Apstraction Layer (HAL)

Status: Open.

#223 In rggen/rggen;

·chili-chips-ba openedon Nov 18, 2024

Allow to specify runtime options by using config file

enhancementNew feature or requestNew feature or request

Status: Open.

#205 In rggen/rggen;

·taichi-ishitani openedon May 8, 2024

PyUVM support

enhancementNew feature or requestNew feature or request

Status: Open.

#203 In rggen/rggen;

·taichi-ishitani openedon Apr 17, 2024

Support Pkl format

Status: Open.

#202 In rggen/rggen;

·taichi-ishitani openedon Apr 11, 2024

Parameterized bit field with

enhancementNew feature or requestNew feature or request

Status: Open.

#201 In rggen/rggen;

·taichi-ishitani openedon Mar 18, 2024

[VHDL] Array port

Status: Open.

#195 In rggen/rggen;

·taichi-ishitani openedon Feb 20, 2024

Specify reset domain

Status: Open.

#193 In rggen/rggen;

·taichi-ishitani openedon Feb 8, 2024

Generate IP-XACT

enhancementNew feature or requestNew feature or request

Status: Open.

#182 In rggen/rggen;

·taichi-ishitani openedon Jan 14, 2024

Provide Python bindings

enhancementNew feature or requestNew feature or request

Status: Open.

#167 In rggen/rggen;

·hpretl openedon Sep 28, 2023

Support SPI as bus interface

Status: Open.

#166 In rggen/rggen;

·hpretl openedon Sep 28, 2023

SVD support

enhancementNew feature or requestNew feature or request

Status: Open.

#153 In rggen/rggen;

·taichi-ishitani openedon Jun 24, 2023

External Registers Issue

Status: Open.

#90 In rggen/rggen;

·davidp135 openedon Nov 11, 2021