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Commitf9ba0a7

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committed
Apple's assembler likes the inlined TAS syntax too, so no reason to
maintain a separate out-of-line version of PPC tas() anymore.Also fix S_UNLOCK for __powerpc64__ platforms.
1 parentb5d0051 commitf9ba0a7

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2 files changed

+13
-41
lines changed

2 files changed

+13
-41
lines changed

‎src/backend/storage/lmgr/s_lock.c‎

Lines changed: 1 addition & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
*
1010
*
1111
* IDENTIFICATION
12-
* $Header: /cvsroot/pgsql/src/backend/storage/lmgr/s_lock.c,v 1.10 2002/11/10 00:33:43 momjian Exp $
12+
* $Header: /cvsroot/pgsql/src/backend/storage/lmgr/s_lock.c,v 1.11 2003/04/20 21:54:34 tgl Exp $
1313
*
1414
*-------------------------------------------------------------------------
1515
*/
@@ -111,39 +111,6 @@ _success:\n\
111111
}
112112
#endif/* __m68k__ */
113113

114-
#if defined(__APPLE__)&& defined(__ppc__)
115-
/* used in darwin. */
116-
/* We key off __APPLE__ here because this function differs from
117-
* the LinuxPPC implementation only in compiler syntax.
118-
*
119-
* NOTE: per the Enhanced PowerPC Architecture manual, v1.0 dated 7-May-2002,
120-
* an isync is a sufficient synchronization barrier after a lwarx/stwcx loop.
121-
*/
122-
staticvoid
123-
tas_dummy()
124-
{
125-
__asm____volatile__(
126-
"\
127-
.globl tas\n\
128-
.globl _tas\n\
129-
_tas:\n\
130-
tas:\n\
131-
lwarxr5,0,r3\n\
132-
cmpwi r5,0\n\
133-
bne fail\n\
134-
addi r5,r5,1\n\
135-
stwcx. r5,0,r3\n\
136-
beq success\n\
137-
fail:li r3,1\n\
138-
blr \n\
139-
success:\n\
140-
isync\n\
141-
li r3,0\n\
142-
blr\n\
143-
");
144-
}
145-
#endif/* __APPLE__ && __ppc__ */
146-
147114
#if defined(__mips__)&& !defined(__sgi)
148115
staticvoid
149116
tas_dummy()

‎src/include/storage/s_lock.h‎

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@
6363
* Portions Copyright (c) 1996-2002, PostgreSQL Global Development Group
6464
* Portions Copyright (c) 1994, Regents of the University of California
6565
*
66-
* $Id: s_lock.h,v 1.105 2003/04/04 06:57:39 tgl Exp $
66+
* $Id: s_lock.h,v 1.106 2003/04/20 21:54:34 tgl Exp $
6767
*
6868
*-------------------------------------------------------------------------
6969
*/
@@ -221,7 +221,12 @@ tas(volatile slock_t *lock)
221221

222222
#endif/* __sparc__ */
223223

224-
#if defined(__powerpc__)|| defined(__powerpc64__)
224+
#if defined(__ppc__)|| defined(__powerpc__)|| defined(__powerpc64__)
225+
#defineTAS(lock) tas(lock)
226+
/*
227+
* NOTE: per the Enhanced PowerPC Architecture manual, v1.0 dated 7-May-2002,
228+
* an isync is a sufficient synchronization barrier after a lwarx/stwcx loop.
229+
*/
225230
static __inline__int
226231
tas(volatileslock_t*lock)
227232
{
@@ -248,7 +253,8 @@ tas(volatile slock_t *lock)
248253
);
249254
return_res;
250255
}
251-
#endif
256+
257+
#endif/* powerpc */
252258

253259

254260
#if defined(__mc68000__)&& defined(__linux__)
@@ -273,10 +279,9 @@ tas(volatile slock_t *lock)
273279
#endif/* defined(__mc68000__) && defined(__linux__) */
274280

275281

276-
#if defined(__ppc__)|| defined(__powerpc__)
282+
#if defined(__ppc__)|| defined(__powerpc__)|| defined(__powerpc64__)
277283
/*
278-
* We currently use out-of-line assembler for TAS on PowerPC; see s_lock.c.
279-
* S_UNLOCK is almost standard but requires a "sync" instruction.
284+
* PowerPC S_UNLOCK is almost standard but requires a "sync" instruction.
280285
*/
281286
#defineS_UNLOCK(lock)\
282287
do \
@@ -285,7 +290,7 @@ do \
285290
*((volatile slock_t *) (lock)) = 0; \
286291
} while (0)
287292

288-
#endif/*defined(__ppc__) || defined(__powerpc__) */
293+
#endif/*powerpc */
289294

290295

291296
#if defined(NEED_VAX_TAS_ASM)

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