Movatterモバイル変換


[0]ホーム

URL:


Skip to content

Navigation Menu

Sign in
Appearance settings

Search code, repositories, users, issues, pull requests...

Provide feedback

We read every piece of feedback, and take your input very seriously.

Saved searches

Use saved searches to filter your results more quickly

Sign up
Appearance settings

Commitf629583

Browse files
author
Neil Conway
committed
Document what the "rep; nop" x86 assembler sequence is actually equivalent
to, and what it is intended to do.
1 parent3ba0fc7 commitf629583

File tree

1 file changed

+24
-1
lines changed

1 file changed

+24
-1
lines changed

‎src/include/storage/s_lock.h

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@
6666
* Portions Copyright (c) 1996-2004, PostgreSQL Global Development Group
6767
* Portions Copyright (c) 1994, Regents of the University of California
6868
*
69-
* $PostgreSQL: pgsql/src/include/storage/s_lock.h,v 1.131 2004/09/24 01:48:43 tgl Exp $
69+
* $PostgreSQL: pgsql/src/include/storage/s_lock.h,v 1.132 2004/10/06 23:41:59 neilc Exp $
7070
*
7171
*-------------------------------------------------------------------------
7272
*/
@@ -138,6 +138,29 @@ tas(volatile slock_t *lock)
138138
static __inline__void
139139
spin_delay(void)
140140
{
141+
/*
142+
* This sequence is equivalent to the PAUSE instruction ("rep" is
143+
* ignored by old IA32 processors if the following instruction is
144+
* not a string operation); the IA-32 Architecture Software
145+
* Developer's Manual, Vol. 3, Section 7.7.2 describes why using
146+
* PAUSE in the inner loop of a spin lock is necessary for good
147+
* performance:
148+
*
149+
* The PAUSE instruction improves the performance of IA-32
150+
* processors supporting Hyper-Threading Technology when
151+
* executing spin-wait loops and other routines where one
152+
* thread is accessing a shared lock or semaphore in a tight
153+
* polling loop. When executing a spin-wait loop, the
154+
* processor can suffer a severe performance penalty when
155+
* exiting the loop because it detects a possible memory order
156+
* violation and flushes the core processor's pipeline. The
157+
* PAUSE instruction provides a hint to the processor that the
158+
* code sequence is a spin-wait loop. The processor uses this
159+
* hint to avoid the memory order violation and prevent the
160+
* pipeline flush. In addition, the PAUSE instruction
161+
* de-pipelines the spin-wait loop to prevent it from
162+
* consuming execution resources excessively.
163+
*/
141164
__asm__ __volatile__(
142165
" rep; nop\n");
143166
}

0 commit comments

Comments
 (0)

[8]ページ先頭

©2009-2025 Movatter.jp