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Align buffer descriptors to cache line boundaries.
Benchmarks has shown that aligning the buffer descriptor array tocache lines is important for scalability; especially on bigger,multi-socket, machines.Currently the array sometimes already happens to be aligned byhappenstance, depending how large previous shared memory allocationswere. That can lead to wildly varying performance results after minorconfiguration changes.In addition to aligning the start of descriptor array, also force thesize of individual descriptors to be of a common cache line size (64bytes). That happens to already be the case on 64bit platforms, butthis way we can change the struct BufferDesc more easily.As the alignment primarily matters in highly concurrent workloadswhich probably all are 64bit these days, and the space wastage ofelement alignment would be a bit more noticeable on 32bit systems, wedon't force the stride to be cacheline sized on 32bit platforms fornow. If somebody does actual performance testing, we can reevaluatethat decision by changing the definition of BUFFERDESC_PADDED_SIZE.Discussion: 20140202151319.GD32123@awork2.anarazel.dePer discussion with Bruce Momjan, Tom Lane, Robert Haas, and PeterGeoghegan.1 parent7142bfb commited12700
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lines changed- contrib/pg_buffercache
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- backend/storage/buffer
- include
- storage
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