@@ -62,22 +62,32 @@ extern slock_tdummy_spinlock;
6262/* This works on any architecture, since it's only talking to GCC itself. */
6363#define pg_compiler_barrier ()__asm__ __volatile__("" : : : "memory")
6464
65- #if defined(__i386__ )|| defined( __x86_64__ ) /* 32 or 64 bit x86 */
65+ #if defined(__i386__ )
6666
6767/*
68- *x86 and x86_64 do not allow loads to be reorded with other loads, or
69- *stores to be reordered with other stores, but a load can be performed
70- *before a subsequent store.
68+ *i386 does not allow loads to be reorded with other loads, or stores to be
69+ * reordered with other stores, but a load can be performed before a subsequent
70+ * store.
7171 *
7272 * "lock; addl" has worked for longer than "mfence".
73+ */
74+ #define pg_memory_barrier ()\
75+ __asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory")
76+ #define pg_read_barrier ()pg_compiler_barrier()
77+ #define pg_write_barrier ()pg_compiler_barrier()
78+
79+ #elif defined(__x86_64__ )/* 64 bit x86 */
80+
81+ /*
82+ * x86_64 has similar ordering characteristics to i386.
7383 *
7484 * Technically, some x86-ish chips support uncached memory access and/or
7585 * special instructions that are weakly ordered. In those cases we'd need
7686 * the read and write barriers to be lfence and sfence. But since we don't
7787 * do those things, a compiler barrier should be enough.
7888 */
7989#define pg_memory_barrier ()\
80- __asm__ __volatile__ ("lock; addl $0,0(%%esp )" : : : "memory")
90+ __asm__ __volatile__ ("lock; addl $0,0(%%rsp )" : : : "memory")
8191#define pg_read_barrier ()pg_compiler_barrier()
8292#define pg_write_barrier ()pg_compiler_barrier()
8393