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Commitb8c6f83

Browse files
author
Alexander Korotkov
committed
LWLock optimization for PowerPC processors
PowerPC processors have quite specific implementation of atomic operations:they are implemented optimistically. If value is changed between our read andwrite, then we have to retry. So, CAS operation on this platform becomespotentially infinite loop. Thus, loop of CAS operations becomes two nestedloops. This patch implements LWLockAttemptLock() as single loop in assembly.That shows great speedup on high concurrent workloads.
1 parent6a2ea08 commitb8c6f83

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‎src/backend/storage/lmgr/lwlock.c

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Original file line numberDiff line numberDiff line change
@@ -768,6 +768,56 @@ GetLWLockIdentifier(uint8 classId, uint16 eventId)
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returnLWLockTrancheArray[eventId]->name;
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}
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#if (defined(__GNUC__)|| defined(__INTEL_COMPILER))&& (defined(__ppc__)|| defined(__powerpc__)|| defined(__ppc64__)|| defined(__powerpc64__))
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/*
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* Special optimization for PowerPC processors: put logic dealing with LWLock
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* state between lwarx/stwcx operations.
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*/
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staticbool
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LWLockAttemptLock(LWLock*lock,LWLockModemode)
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{
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uint32mask,increment;
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boolresult;
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AssertArg(mode==LW_EXCLUSIVE||mode==LW_SHARED);
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if (mode==LW_EXCLUSIVE)
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{
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mask=LW_LOCK_MASK;
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increment=LW_VAL_EXCLUSIVE;
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}
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else
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{
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mask=LW_VAL_EXCLUSIVE;
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increment=LW_VAL_SHARED;
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}
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__asm__ __volatile__(
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"0:lwarx 3,0,%4\n"
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"and 4,3,%2\n"
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"cmpwi 4,0\n"
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"bne- 1f\n"
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"add 3,3,%3\n"
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"stwcx. 3,0,%4\n"
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"bne- 0b\n"
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"li %0,0\n"
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"b 2f\n"
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"1: li %0,1\n"
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#ifdefUSE_PPC_LWSYNC
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"2:lwsync\n"
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#else
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"2:isync\n"
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#endif
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:"=&r"(result),"+m"(lock->state)
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:"r"(mask),"r"(increment),"r"(&lock->state)
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:"memory","cc","r3","r4");
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returnresult;
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}
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#else
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/*
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* Internal function that tries to atomically acquire the lwlock in the passed
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* in mode.
@@ -910,6 +960,8 @@ LWLockWaitListUnlock(LWLock *lock)
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Assert(old_state&LW_FLAG_LOCKED);
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}
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#endif
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/*
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* Wakeup all the lockers that currently have a chance to acquire the lock.
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*/

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