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Commit40dde82

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Fix spinlock assembly code for MIPS so it works on MIPS r6.
Original MIPS-I processors didn't have the LL/SC instructions (nor anyother userland synchronization primitive). If the build toolchaintargets that ISA variant by default, as an astonishingly large fractionof MIPS platforms still do, the assembler won't take LL/SC withoutcoercion in the form of a ".set mips2" instruction. But we issued thatunconditionally, making it an ISA downgrade for chips later than MIPS2.That breaks things for the latest MIPS r6 ISA, which encodes theseinstructions differently. Adjust the code so we don't change ISA levelif it's >= 2.Note that this patch doesn't change what happens on an actual MIPS-Iprocessor: either the kernel will emulate these instructionstransparently, or you'll get a SIGILL failure. That tradeoff seemedfine in 2002 when this code was added (cf3cbe6b2), and it's evenmore so today when MIPS-I is basically extinct. But let's add acomment about that.YunQiang Su (with cosmetic adjustments by me). Back-patch to allsupported branches.Discussion:https://postgr.es/m/15844-8f62fe7e163939b3@postgresql.org
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‎src/include/storage/s_lock.h

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -598,14 +598,31 @@ tas(volatile slock_t *lock)
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#if defined(__mips__)&& !defined(__sgi)/* non-SGI MIPS */
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/* Note: on SGI we use the OS' mutex ABI, see below */
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/* Note: R10000 processors require a separate SYNC */
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#defineHAS_TEST_AND_SET
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typedefunsignedintslock_t;
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#defineTAS(lock) tas(lock)
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/*
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* Original MIPS-I processors lacked the LL/SC instructions, but if we are
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* so unfortunate as to be running on one of those, we expect that the kernel
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* will handle the illegal-instruction traps and emulate them for us. On
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* anything newer (and really, MIPS-I is extinct) LL/SC is the only sane
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* choice because any other synchronization method must involve a kernel
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* call. Unfortunately, many toolchains still default to MIPS-I as the
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* codegen target; if the symbol __mips shows that that's the case, we
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* have to force the assembler to accept LL/SC.
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*
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* R10000 and up processors require a separate SYNC, which has the same
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* issues as LL/SC.
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*/
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#if__mips<2
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#defineMIPS_SET_MIPS2" .set mips2 \n"
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#else
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#defineMIPS_SET_MIPS2
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#endif
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static __inline__int
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tas(volatileslock_t*lock)
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{
@@ -615,7 +632,7 @@ tas(volatile slock_t *lock)
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__asm__ __volatile__(
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" .set push \n"
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" .set mips2 \n"
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MIPS_SET_MIPS2
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" .set noreorder \n"
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" .set nomacro \n"
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" ll %0, %2 \n"
@@ -637,7 +654,7 @@ do \
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{ \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set mips2 \n" \
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MIPS_SET_MIPS2 \
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" .set noreorder \n" \
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" .set nomacro \n" \
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" sync \n" \

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