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Commit375d852

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Keep heavily-contended fields in XLogCtlInsert on different cache lines.
Performance testing shows that if the insertpos_lck spinlock and the fieldsthat it protects are on the same cache line with other variables that arefrequently accessed, the false sharing can hurt performance a lot. Keepthem apart by adding some padding.
1 parentcc52d5b commit375d852

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2 files changed

+23
-3
lines changed

2 files changed

+23
-3
lines changed

‎src/backend/access/transam/xlog.c‎

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -408,7 +408,7 @@ typedef struct
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typedefunionXLogInsertSlotPadded
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{
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XLogInsertSlotslot;
411-
charpad[64];
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charpad[CACHE_LINE_SIZE];
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}XLogInsertSlotPadded;
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/*
@@ -428,8 +428,14 @@ typedef struct XLogCtlInsert
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uint64CurrBytePos;
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uint64PrevBytePos;
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431-
/* insertion slots, see above for details */
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XLogInsertSlotPadded*insertSlots;
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/*
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* Make sure the above heavily-contended spinlock and byte positions are
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* on their own cache line. In particular, the RedoRecPtr and full page
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* write variables below should be on a different cache line. They are
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* read on every WAL insertion, but updated rarely, and we don't want
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* those reads to steal the cache line containing Curr/PrevBytePos.
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*/
438+
charpad[CACHE_LINE_SIZE];
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/*
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* fullPageWrites is the master copy used by all backends to determine
@@ -455,6 +461,9 @@ typedef struct XLogCtlInsert
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boolexclusiveBackup;
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intnonExclusiveBackups;
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XLogRecPtrlastBackupStart;
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/* insertion slots, see XLogInsertSlot struct above for details */
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XLogInsertSlotPadded*insertSlots;
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}XLogCtlInsert;
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460469
/*

‎src/include/pg_config_manual.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -199,6 +199,17 @@
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#defineUSE_PPC_LWSYNC
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#endif
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/*
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* Assumed cache line size. This doesn't affect correctness, but can be
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* used for low-level optimizations. Currently, this is only used to pad
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* some data structures in xlog.c, to ensure that highly-contended fields
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* are on different cache lines. Too small a value can hurt performance due
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* to false sharing, while the only downside of too large a value is a few
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* bytes of wasted memory. The default is 128, which should be large enough
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* for all supported platforms.
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*/
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#defineCACHE_LINE_SIZE128
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/*
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*------------------------------------------------------------------------
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* The following symbols are for enabling debugging code, not for

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