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Commitf18cad9

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Fix atomic ops inline x86 inline assembly for older 32bit gccs.
Some x86 32bit versions of gcc apparently generate references to thenonexistant %sil register when using when using the r inputconstraint, but not with the =q constraint. The latter restrictsallocations to a/b/c/d which should all work.
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‎src/include/port/atomics/arch-x86.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -175,7 +175,7 @@ pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
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"lock\n"
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"cmpxchgl%4,%5\n"
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" setz%2\n"
178-
:"=a" (*expected),"=m"(ptr->value),"=r" (ret)
178+
:"=a" (*expected),"=m"(ptr->value),"=q" (ret)
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:"a" (*expected),"r" (newval),"m"(ptr->value)
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:"memory","cc");
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return (bool)ret;
@@ -212,7 +212,7 @@ pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
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"lock\n"
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"cmpxchgq%4,%5\n"
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" setz%2\n"
215-
:"=a" (*expected),"=m"(ptr->value),"=r" (ret)
215+
:"=a" (*expected),"=m"(ptr->value),"=q" (ret)
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:"a" (*expected),"r" (newval),"m"(ptr->value)
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:"memory","cc");
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return (bool)ret;

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