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Commitd0b7ffc

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Fix spinlock implementation for some !solaris sparc platforms.
Some Sparc CPUs can be run in various coherence models, ranging fromRMO (relaxed) over PSO (partial) to TSO (total). Solaris has alwaysrun CPUs in TSO mode while in userland, but linux didn't use to andthe various *BSDs still don't. Unfortunately the sparc TAS/S_UNLOCKwere only correct under TSO. Fix that by adding the necessary memorybarrier instructions. On sparcv8+, which should be all relevant CPUs,these are treated as NOPs if the current consistency model doesn'trequire the barriers.Discussion: 20140630222854.GW26930@awork2.anarazel.deWill be backpatched to all released branches once a few buildfarmcycles haven't shown up problems. As I've no access to sparc, this isblindly written.
1 parent886b58b commitd0b7ffc

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2 files changed

+50
-1
lines changed

2 files changed

+50
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‎src/backend/port/tas/sunstudio_sparc.s

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@@ -37,6 +37,8 @@ pg_atomic_cas:
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!
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!http://cvs.opensolaris.org/source/xref/on/usr/src/lib/libc/sparc/threads/sparc.il
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!
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!NB: We're assuming we're running on a TSO system here - solaris
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! userland luckily always has done so.
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#if defined(__sparcv9) || defined(__sparcv8plus)
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cas [%o0],%o2,%o1

‎src/include/storage/s_lock.h

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@@ -383,6 +383,12 @@ tas(volatile slock_t *lock)
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#if defined(__sparc__)/* Sparc */
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/*
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* Solaris has always run sparc processors in TSO (total store) mode, but
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* linux didn't use to and the *BSDs still don't. So, be careful about
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* acquire/release semantics. The CPU will treat superflous membars as NOPs,
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* so it's just code space.
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*/
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#defineHAS_TEST_AND_SET
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typedefunsignedcharslock_t;
@@ -404,9 +410,50 @@ tas(volatile slock_t *lock)
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:"=r"(_res),"+m"(*lock)
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:"r"(lock)
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:"memory");
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#if defined(__sparcv7)
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/*
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* No stbar or membar available, luckily no actually produced hardware
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* requires a barrier.
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*/
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#elif defined(__sparcv8)
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/* stbar is available (and required for both PSO, RMO), membar isn't */
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__asm__ __volatile__ ("stbar \n":::"memory");
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#else
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/*
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* #LoadStore (RMO) | #LoadLoad (RMO) together are the appropriate acquire
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* barrier for sparcv8+ upwards.
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*/
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__asm__ __volatile__ ("membar #LoadStore | #LoadLoad \n":::"memory");
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#endif
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return (int)_res;
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}
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#if defined(__sparcv7)
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/*
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* No stbar or membar available, luckily no actually produced hardware
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* requires a barrier.
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*/
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#defineS_UNLOCK(lock)(*((volatile slock_t *) (lock)) = 0)
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#elif__sparcv8
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/* stbar is available (and required for both PSO, RMO), membar isn't */
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#defineS_UNLOCK(lock)\
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do \
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{ \
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__asm__ __volatile__ ("stbar \n":::"memory"); \
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*((volatile slock_t *) (lock)) = 0; \
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} while (0)
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#else
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/*
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* #LoadStore (RMO) | #StoreStore (RMO, PSO) together are the appropriate
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* release barrier for sparcv8+ upwards.
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*/
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do \
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{ \
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__asm__ __volatile__ ("membar #LoadStore | #StoreStore \n":::"memory"); \
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*((volatileslock_t*) (lock))=0; \
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}while (0)
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#endif
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#endif/* __sparc__ */
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@@ -907,7 +954,7 @@ typedef int slock_t;
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#endif/* _AIX */
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/* These are ins_lock.c */
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/* These are insunstudio_(sparc|x86).s */
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#if defined(sun3)/* Sun3 */

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