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Declare aarch64 has single copy atomicity for 8 byte values.

Architecture Reference Manual for ARMv8 B2.2.1 [1]For explicit memory effects generated from an Exception level thefollowing rules apply:- A read that is generated by a load instruction that loads a singlegeneral-purpose register and is aligned to the size of the read in theinstruction is single-copy atomic.- A write that is generated by a store instruction that stores a singlegeneral-purpose register and is aligned to the size of the write in theinstruction is single-copy atomic.[1]https://documentation-service.arm.com/static/61fbe8f4fa8173727a1b734e https://developer.arm.com/documentation/ddi0487/latestAuthor: Yura Sokolov <y.sokolov@postgrespro.ru>Reviewed-by: Thomas Munro <thomas.munro@gmail.com>Reviewed-by: Alexander Korotkov <aekorotkov@gmail.com>Discussion:https://postgr.es/m/f7f3f0febe27862711f924a7b0f39e065e547f4b.camel%40postgrespro.ruDiscussion:https://postgr.es/m/CA%2BhUKGKyJf7kwYkqDgzTE26Ra1m9nvM%3Deds2RSSu7WSL-r2wKw%40mail.gmail.com

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Original file line number	Diff line number	Diff line change
`@@ -23,4 +23,10 @@`
`23`	`23`	`*/`
`24`	`24`	`#if !defined(__aarch64__)&& !defined(__aarch64)`
`25`	`25`	`#definePG_DISABLE_64_BIT_ATOMICS`
	`26`	`+#else`
	`27`	`+/*`
	`28`	`+ * Architecture Reference Manual for ARMv8 states aligned read/write to/from`
	`29`	`+ * general purpose register is atomic.`
	`30`	`+ */`
	`31`	`+#definePG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY`
`26`	`32`	`#endif/* __aarch64__ \|\| __aarch64 */`

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