Commit967ce57

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Remove unused symbol __aarch64

This was added as a possible variant of __aarch64__ back when 64-bitARM was vaporware. It hasn't shown up in the wild since then, so remove.Nathan BossartDiscussion:https://www.postgresql.org/message-id/CAFBsxsEN5nW3uRh%3Djrs-QexDrC1btu0ZfriD3FFfb%3D3J6tAngg%40mail.gmail.com

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Lines changed: 1 addition & 2 deletions

Original file line number	Diff line number	Diff line change
`@@ -63,8 +63,7 @@`
`63`	`63`	`* compiler barrier.`
`64`	`64`	`*`
`65`	`65`	`*/`
`66`		`-#if defined(__arm__)\|\| defined(__arm)\|\| \`
`67`		`-defined(__aarch64__)\|\| defined(__aarch64)`
	`66`	`+#if defined(__arm__)\|\| defined(__arm)\|\| defined(__aarch64__)`
`68`	`67`	`#include"port/atomics/arch-arm.h"`
`69`	`68`	`#elif defined(__i386__)\|\| defined(__i386)\|\| defined(__x86_64__)`
`70`	`69`	`#include"port/atomics/arch-x86.h"`

Lines changed: 2 additions & 2 deletions

Original file line number	Diff line number	Diff line change
`@@ -21,12 +21,12 @@`
`21`	`21`	`* 64 bit atomics on ARM32 are implemented using kernel fallbacks and thus`
`22`	`22`	`* might be slow, so disable entirely. On ARM64 that problem doesn't exist.`
`23`	`23`	`*/`
`24`		`-#if !defined(__aarch64__)&& !defined(__aarch64)`
	`24`	`+#if !defined(__aarch64__)`
`25`	`25`	`#definePG_DISABLE_64_BIT_ATOMICS`
`26`	`26`	`#else`
`27`	`27`	`/*`
`28`	`28`	`* Architecture Reference Manual for ARMv8 states aligned read/write to/from`
`29`	`29`	`* general purpose register is atomic.`
`30`	`30`	`*/`
`31`	`31`	`#definePG_HAVE_8BYTE_SINGLE_COPY_ATOMICITY`
`32`		`-#endif/* __aarch64__\|\| __aarch64*/`
	`32`	`+#endif/* __aarch64__ */`

Lines changed: 4 additions & 4 deletions

Original file line number	Diff line number	Diff line change
`@@ -256,7 +256,7 @@ spin_delay(void)`
`256`	`256`	`* We use the int-width variant of the builtin because it works on more chips`
`257`	`257`	`* than other widths.`
`258`	`258`	`*/`
`259`		`-#if defined(__arm__)\|\| defined(__arm)\|\| defined(__aarch64__)\|\| defined(__aarch64)`
	`259`	`+#if defined(__arm__)\|\| defined(__arm)\|\| defined(__aarch64__)`
`260`	`260`	`#ifdefHAVE_GCC__SYNC_INT32_TAS`
`261`	`261`	`#defineHAS_TEST_AND_SET`
`262`	`262`
`@@ -277,7 +277,7 @@ tas(volatile slock_t *lock)`
`277`	`277`	`* high-core-count ARM64 processors. It seems mostly a wash for smaller gear,`
`278`	`278`	`* and ISB doesn't exist at all on pre-v7 ARM chips.`
`279`	`279`	`*/`
`280`		`-#if defined(__aarch64__)\|\| defined(__aarch64)`
	`280`	`+#if defined(__aarch64__)`
`281`	`281`
`282`	`282`	`#defineSPIN_DELAY() spin_delay()`
`283`	`283`
`@@ -288,9 +288,9 @@ spin_delay(void)`
`288`	`288`	`" isb;\n");`
`289`	`289`	`}`
`290`	`290`
`291`		`-#endif/* __aarch64__\|\| __aarch64*/`
	`291`	`+#endif/* __aarch64__ */`
`292`	`292`	`#endif/* HAVE_GCC__SYNC_INT32_TAS */`
`293`		`-#endif/* __arm__ \|\| __arm \|\| __aarch64__\|\| __aarch64*/`
	`293`	`+#endif/* __arm__ \|\| __arm \|\| __aarch64__ */`
`294`	`294`
`295`	`295`
`296`	`296`	`/*`

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