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Mark x86's memory barrier inline assembly as clobbering the cpu flags.

x86's memory barrier assembly was marked as clobbering "memory" butnot "cc" even though 'addl' sets various flags. As it turns out gcc onx86 implicitly assumes "cc" on every inline assembler statement, soit's not a bug. But as that's poorly documented and might get copiedto architectures or compilers where that's not the case, it seemsbetter to be precise.Discussion: 20140919100016.GH4277@alap3.anarazel.deTo keep the code common, backpatch to 9.2 where explicit memorybarriers were introduced.

1 parent710524e commit855cabbCopy full SHA for 855cabb

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src/include/storage
- barrier.h

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`‎src/include/storage/barrier.h`

Lines changed: 2 additions & 2 deletions

Original file line number	Diff line number	Diff line change
`@@ -70,7 +70,7 @@ extern slock_t dummy_spinlock;`
`70`	`70`	`* "lock; addl" has worked for longer than "mfence".`
`71`	`71`	`*/`
`72`	`72`	`#definepg_memory_barrier()\`
`73`		`-__asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory")`
	`73`	`+__asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory", "cc")`
`74`	`74`	`#definepg_read_barrier()pg_compiler_barrier()`
`75`	`75`	`#definepg_write_barrier()pg_compiler_barrier()`
`76`	`76`	`#elif defined(__x86_64__)/* 64 bit x86 */`
`@@ -84,7 +84,7 @@ extern slock_t dummy_spinlock;`
`84`	`84`	`* do those things, a compiler barrier should be enough.`
`85`	`85`	`*/`
`86`	`86`	`#definepg_memory_barrier()\`
`87`		`-__asm__ __volatile__ ("lock; addl $0,0(%%rsp)" : : : "memory")`
	`87`	`+__asm__ __volatile__ ("lock; addl $0,0(%%rsp)" : : : "memory", "cc")`
`88`	`88`	`#definepg_read_barrier()pg_compiler_barrier()`
`89`	`89`	`#definepg_write_barrier()pg_compiler_barrier()`
`90`	`90`	`#elif defined(__ia64__)\|\| defined(__ia64)`

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Commit855cabb

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`‎src/include/storage/barrier.h`

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