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Commit83aadbe

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Require memory barrier support.
Previously we had a fallback implementation that made a harmless systemcall, based on the assumption that system calls must contain a memorybarrier. That shouldn't be reached on any current system, and it seemshighly likely that we can easily find out how to request explicit memorybarriers, if we've already had to find out how to do atomics on ahypothetical new system.Removed comments and a function name referred to a spinlock used forfallback memory barriers, but that changed in1b468a1, which left somemisleading words behind in a few places.Reviewed-by: Heikki Linnakangas <hlinnaka@iki.fi>Suggested-by: Andres Freund <andres@anarazel.de>Discussion:https://postgr.es/m/721bf39a-ed8a-44b0-8b8e-be3bd81db748%40technowledgy.deDiscussion:https://postgr.es/m/3351991.1697728588%40sss.pgh.pa.us
1 parenta011dc3 commit83aadbe

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4 files changed

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-49
lines changed

4 files changed

+4
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lines changed

‎src/backend/port/atomics.c‎

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@@ -17,29 +17,6 @@
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#include"port/atomics.h"
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#include"storage/spin.h"
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#ifdefPG_HAVE_MEMORY_BARRIER_EMULATION
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#ifdefWIN32
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#error "barriers are required (and provided) on WIN32 platforms"
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#endif
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#include<signal.h>
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#endif
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#ifdefPG_HAVE_MEMORY_BARRIER_EMULATION
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void
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pg_spinlock_barrier(void)
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{
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/*
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* NB: we have to be reentrant here, some barriers are placed in signal
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* handlers.
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*
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* We use kill(0) for the fallback barrier as we assume that kernels on
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* systems old enough to require fallback barrier support will include an
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* appropriate barrier while checking the existence of the postmaster pid.
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*/
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(void)kill(PostmasterPid,0);
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}
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#endif
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#ifdefPG_HAVE_ATOMIC_U64_SIMULATION
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‎src/include/port/atomics.h‎

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#if !defined(pg_compiler_barrier_impl)
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#error "could not find an implementation of pg_compiler_barrier"
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#endif
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#if !defined(pg_memory_barrier_impl)
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#error "could not find an implementation of pg_memory_barrier_impl"
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#endif
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/*
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* Provide a spinlock-based implementation of the 64 bit variants, if

‎src/include/port/atomics/fallback.h‎

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#error "should be included via atomics.h"
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#endif
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#ifndefpg_memory_barrier_impl
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/*
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* If we have no memory barrier implementation for this architecture, we
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* fall back to acquiring and releasing a spinlock.
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*
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* It's not self-evident that every possible legal implementation of a
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* spinlock acquire-and-release would be equivalent to a full memory barrier.
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* For example, I'm not sure that Itanium's acq and rel add up to a full
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* fence. But all of our actual implementations seem OK in this regard.
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*/
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#definePG_HAVE_MEMORY_BARRIER_EMULATION
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externvoidpg_spinlock_barrier(void);
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#definepg_memory_barrier_impl pg_spinlock_barrier
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#endif
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#if !defined(PG_HAVE_ATOMIC_U64_SUPPORT)
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‎src/include/port/atomics/generic.h‎

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@@ -135,19 +135,9 @@ pg_atomic_unlocked_test_flag_impl(volatile pg_atomic_flag *ptr)
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staticinlinevoid
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pg_atomic_clear_flag_impl(volatilepg_atomic_flag*ptr)
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{
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/*
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* Use a memory barrier + plain write if we have a native memory
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* barrier. But don't do so if memory barriers use spinlocks - that'd lead
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* to circularity if flags are used to implement spinlocks.
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*/
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#ifndefPG_HAVE_MEMORY_BARRIER_EMULATION
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/* XXX: release semantics suffice? */
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pg_memory_barrier_impl();
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pg_atomic_write_u32_impl(ptr,0);
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#else
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uint32value=1;
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pg_atomic_compare_exchange_u32_impl(ptr,&value,0);
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#endif
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}
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#elif !defined(PG_HAVE_ATOMIC_TEST_SET_FLAG)

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