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Commit3d0b4b1

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Use a non-locking initial test in TAS_SPIN on AArch64.
Our testing showed that this is helpful at sufficiently highcontention levels and doesn't hurt performance on smaller machines.The new TAS_SPIN macro for AArch64 is identical to the ones addedfor PPC and x86_64 (see commitsbc2a050 andb03d196).Reported-by: Salvatore DipietroReviewed-by: Jingtang Zhang, Andres FreundTested-by: Tom LaneDiscussion:https://postgr.es/m/ZxgDEb_VpWyNZKB_%40nathan
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‎src/include/storage/s_lock.h

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -263,18 +263,24 @@ tas(volatile slock_t *lock)
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#defineS_UNLOCK(lock) __sync_lock_release(lock)
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#if defined(__aarch64__)
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/*
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* Using an ISB instruction to delay in spinlock loops appears beneficial on
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* high-core-count ARM64 processors. It seems mostly a wash for smaller gear,
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* and ISB doesn't exist at all on pre-v7 ARM chips.
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* On ARM64, it's a win to use a non-locking test before the TAS proper. It
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* may be a win on 32-bit ARM, too, but nobody's tested it yet.
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*/
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#if defined(__aarch64__)
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#defineTAS_SPIN(lock)(*(lock) ? 1 : TAS(lock))
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#defineSPIN_DELAY() spin_delay()
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static __inline__void
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spin_delay(void)
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{
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/*
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* Using an ISB instruction to delay in spinlock loops appears beneficial
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* on high-core-count ARM64 processors. It seems mostly a wash for smaller
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* gear, and ISB doesn't exist at all on pre-v7 ARM chips.
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*/
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__asm__ __volatile__(
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" isb;\n");
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}

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