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Commit0ad5b48

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Remove HP/Intel Itanium support.
This CPU architecture has been discontinued. We already removed HP-UXsupport, we never supported Windows/Itanium, and the open sourceoperating systems that a vintage hardware owner might hope to run haveall either ended Itanium support or never fully released support (NetBSDmay eventually). The extra code we carry for this rare ISA is nowuntested. It seems like a good time to remove it.Reviewed-by: Tom Lane <tgl@sss.pgh.pa.us>Reviewed-by: Andres Freund <andres@anarazel.de>Discussion:https://postgr.es/m/1415825.1656893299%40sss.pgh.pa.us
1 parent9db300c commit0ad5b48

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9 files changed

+2
-177
lines changed

9 files changed

+2
-177
lines changed

‎doc/src/sgml/installation.sgml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2125,7 +2125,7 @@ export MANPATH
21252125

21262126
<para>
21272127
In general, <productname>PostgreSQL</productname> can be expected to work on
2128-
these CPU architectures: x86, x86_64,IA64,PowerPC,
2128+
these CPU architectures: x86, x86_64, PowerPC,
21292129
PowerPC 64, S/390, S/390x, Sparc, Sparc 64, ARM, MIPS, MIPSEL,
21302130
and PA-RISC. Code support exists for M68K, M32R, and VAX, but these
21312131
architectures are not known to have been tested recently. It is often

‎src/backend/tcop/postgres.c‎

Lines changed: 0 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -132,13 +132,6 @@ static long max_stack_depth_bytes = 100 * 1024L;
132132
*/
133133
staticchar*stack_base_ptr=NULL;
134134

135-
/*
136-
* On IA64 we also have to remember the register stack base.
137-
*/
138-
#if defined(__ia64__)|| defined(__ia64)
139-
staticchar*register_stack_base_ptr=NULL;
140-
#endif
141-
142135
/*
143136
* Flag to keep track of whether we have started a transaction.
144137
* For extended query protocol this has to be remembered across messages.
@@ -3392,41 +3385,6 @@ ProcessInterrupts(void)
33923385
ProcessLogMemoryContextInterrupt();
33933386
}
33943387

3395-
3396-
/*
3397-
* IA64-specific code to fetch the AR.BSP register for stack depth checks.
3398-
*
3399-
* We currently support gcc and icc here.
3400-
*
3401-
* Note: while icc accepts gcc asm blocks on x86[_64], this is not true on
3402-
* ia64 (at least not in icc versions before 12.x). So we have to carry a
3403-
* separate implementation for it.
3404-
*/
3405-
#if defined(__ia64__)|| defined(__ia64)
3406-
3407-
#if defined(__INTEL_COMPILER)
3408-
/* icc */
3409-
#include<asm/ia64regs.h>
3410-
#defineia64_get_bsp() ((char *) __getReg(_IA64_REG_AR_BSP))
3411-
#else
3412-
/* gcc */
3413-
static __inline__char*
3414-
ia64_get_bsp(void)
3415-
{
3416-
char*ret;
3417-
3418-
/* the ;; is a "stop", seems to be required before fetching BSP */
3419-
__asm__ __volatile__(
3420-
";;\n"
3421-
"mov%0=ar.bsp\n"
3422-
:"=r"(ret));
3423-
3424-
returnret;
3425-
}
3426-
#endif
3427-
#endif/* IA64 */
3428-
3429-
34303388
/*
34313389
* set_stack_base: set up reference point for stack depth checking
34323390
*
@@ -3440,12 +3398,7 @@ set_stack_base(void)
34403398
#endif
34413399
pg_stack_base_told;
34423400

3443-
#if defined(__ia64__)|| defined(__ia64)
3444-
old.stack_base_ptr=stack_base_ptr;
3445-
old.register_stack_base_ptr=register_stack_base_ptr;
3446-
#else
34473401
old=stack_base_ptr;
3448-
#endif
34493402

34503403
/*
34513404
* Set up reference point for stack depth checking. On recent gcc we use
@@ -3457,9 +3410,6 @@ set_stack_base(void)
34573410
#else
34583411
stack_base_ptr=&stack_base;
34593412
#endif
3460-
#if defined(__ia64__)|| defined(__ia64)
3461-
register_stack_base_ptr=ia64_get_bsp();
3462-
#endif
34633413

34643414
returnold;
34653415
}
@@ -3476,12 +3426,7 @@ set_stack_base(void)
34763426
void
34773427
restore_stack_base(pg_stack_base_tbase)
34783428
{
3479-
#if defined(__ia64__)|| defined(__ia64)
3480-
stack_base_ptr=base.stack_base_ptr;
3481-
register_stack_base_ptr=base.register_stack_base_ptr;
3482-
#else
34833429
stack_base_ptr=base;
3484-
#endif
34853430
}
34863431

34873432
/*
@@ -3538,22 +3483,6 @@ stack_is_too_deep(void)
35383483
stack_base_ptr!=NULL)
35393484
return true;
35403485

3541-
/*
3542-
* On IA64 there is a separate "register" stack that requires its own
3543-
* independent check. For this, we have to measure the change in the
3544-
* "BSP" pointer from PostgresMain to here. Logic is just as above,
3545-
* except that we know IA64's register stack grows up.
3546-
*
3547-
* Note we assume that the same max_stack_depth applies to both stacks.
3548-
*/
3549-
#if defined(__ia64__)|| defined(__ia64)
3550-
stack_depth= (long) (ia64_get_bsp()-register_stack_base_ptr);
3551-
3552-
if (stack_depth>max_stack_depth_bytes&&
3553-
register_stack_base_ptr!=NULL)
3554-
return true;
3555-
#endif/* IA64 */
3556-
35573486
return false;
35583487
}
35593488

‎src/include/miscadmin.h‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -279,15 +279,7 @@ extern PGDLLIMPORT bool VacuumCostActive;
279279

280280
/* in tcop/postgres.c */
281281

282-
#if defined(__ia64__)|| defined(__ia64)
283-
typedefstruct
284-
{
285-
char*stack_base_ptr;
286-
char*register_stack_base_ptr;
287-
}pg_stack_base_t;
288-
#else
289282
typedefchar*pg_stack_base_t;
290-
#endif
291283

292284
externpg_stack_base_tset_stack_base(void);
293285
externvoidrestore_stack_base(pg_stack_base_tbase);

‎src/include/port/atomics.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,6 @@
6868
#include"port/atomics/arch-arm.h"
6969
#elif defined(__i386__)|| defined(__i386)|| defined(__x86_64__)
7070
#include"port/atomics/arch-x86.h"
71-
#elif defined(__ia64__)|| defined(__ia64)
72-
#include"port/atomics/arch-ia64.h"
7371
#elif defined(__ppc__)|| defined(__powerpc__)|| defined(__ppc64__)|| defined(__powerpc64__)
7472
#include"port/atomics/arch-ppc.h"
7573
#elif defined(__hppa)|| defined(__hppa__)

‎src/include/port/atomics/arch-ia64.h‎

Lines changed: 0 additions & 27 deletions
This file was deleted.

‎src/include/port/atomics/generic-msvc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
8686
returnret;
8787
}
8888

89-
/* Only implemented onitanium and64bit builds */
89+
/* Only implemented on 64bit builds */
9090
#ifdef_WIN64
9191
#pragma intrinsic(_InterlockedExchangeAdd64)
9292

‎src/include/storage/s_lock.h‎

Lines changed: 0 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -250,71 +250,6 @@ spin_delay(void)
250250
#endif/* __x86_64__ */
251251

252252

253-
#if defined(__ia64__)|| defined(__ia64)
254-
/*
255-
* Intel Itanium, gcc or Intel's compiler.
256-
*
257-
* Itanium has weak memory ordering, but we rely on the compiler to enforce
258-
* strict ordering of accesses to volatile data. In particular, while the
259-
* xchg instruction implicitly acts as a memory barrier with 'acquire'
260-
* semantics, we do not have an explicit memory fence instruction in the
261-
* S_UNLOCK macro. We use a regular assignment to clear the spinlock, and
262-
* trust that the compiler marks the generated store instruction with the
263-
* ".rel" opcode.
264-
*
265-
* Testing shows that assumption to hold on gcc, although I could not find
266-
* any explicit statement on that in the gcc manual. In Intel's compiler,
267-
* the -m[no-]serialize-volatile option controls that, and testing shows that
268-
* it is enabled by default.
269-
*
270-
* While icc accepts gcc asm blocks on x86[_64], this is not true on ia64
271-
* (at least not in icc versions before 12.x). So we have to carry a separate
272-
* compiler-intrinsic-based implementation for it.
273-
*/
274-
#defineHAS_TEST_AND_SET
275-
276-
typedefunsignedintslock_t;
277-
278-
#defineTAS(lock) tas(lock)
279-
280-
/* On IA64, it's a win to use a non-locking test before the xchg proper */
281-
#defineTAS_SPIN(lock)(*(lock) ? 1 : TAS(lock))
282-
283-
#ifndef__INTEL_COMPILER
284-
285-
static __inline__int
286-
tas(volatileslock_t*lock)
287-
{
288-
longintret;
289-
290-
__asm__ __volatile__(
291-
"xchg4 %0=%1,%2\n"
292-
:"=r"(ret),"+m"(*lock)
293-
:"r"(1)
294-
:"memory");
295-
return (int)ret;
296-
}
297-
298-
#else/* __INTEL_COMPILER */
299-
300-
static __inline__int
301-
tas(volatileslock_t*lock)
302-
{
303-
intret;
304-
305-
ret=_InterlockedExchange(lock,1);/* this is a xchg asm macro */
306-
307-
returnret;
308-
}
309-
310-
/* icc can't use the regular gcc S_UNLOCK() macro either in this case */
311-
#defineS_UNLOCK(lock)\
312-
do { __memory_barrier(); *(lock) = 0; } while (0)
313-
314-
#endif/* __INTEL_COMPILER */
315-
#endif/* __ia64__ || __ia64 */
316-
317-
318253
/*
319254
* On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
320255
*

‎src/tools/pginclude/cpluspluscheck‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,6 @@ do
8181
# relevant to our platform will be included by atomics.h.
8282
test"$f" = src/include/port/atomics/arch-arm.h&&continue
8383
test"$f" = src/include/port/atomics/arch-hppa.h&&continue
84-
test"$f" = src/include/port/atomics/arch-ia64.h&&continue
8584
test"$f" = src/include/port/atomics/arch-ppc.h&&continue
8685
test"$f" = src/include/port/atomics/arch-x86.h&&continue
8786
test"$f" = src/include/port/atomics/fallback.h&&continue

‎src/tools/pginclude/headerscheck‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,6 @@ do
7777
# relevant to our platform will be included by atomics.h.
7878
test"$f" = src/include/port/atomics/arch-arm.h&&continue
7979
test"$f" = src/include/port/atomics/arch-hppa.h&&continue
80-
test"$f" = src/include/port/atomics/arch-ia64.h&&continue
8180
test"$f" = src/include/port/atomics/arch-ppc.h&&continue
8281
test"$f" = src/include/port/atomics/arch-x86.h&&continue
8382
test"$f" = src/include/port/atomics/fallback.h&&continue

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