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Use ISB as a spin-delay instruction on ARM64.

This seems beneficial on high-core-count machines, and not harmfulon lesser hardware. However, older ARM32 gear doesn't have thisinstruction, so restrict the patch to ARM64.Geoffrey BlakeDiscussion:https://postgr.es/m/78338F29-9D7F-4DC8-BD71-E9674CE71425@amazon.com

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Original file line number	Diff line number	Diff line change
`@@ -337,6 +337,23 @@ tas(volatile slock_t *lock)`
`337`	`337`
`338`	`338`	`#defineS_UNLOCK(lock) __sync_lock_release(lock)`
`339`	`339`
	`340`	`+/*`
	`341`	`+ * Using an ISB instruction to delay in spinlock loops appears beneficial on`
	`342`	`+ * high-core-count ARM64 processors. It seems mostly a wash for smaller gear,`
	`343`	`+ * and ISB doesn't exist at all on pre-v7 ARM chips.`
	`344`	`+ */`
	`345`	`+#if defined(__aarch64__)\|\| defined(__aarch64)`
	`346`	`+`
	`347`	`+#defineSPIN_DELAY() spin_delay()`
	`348`	`+`
	`349`	`+static __inline__void`
	`350`	`+spin_delay(void)`
	`351`	`+{`
	`352`	`+__asm__ __volatile__(`
	`353`	`+" isb;\n");`
	`354`	`+}`
	`355`	`+`
	`356`	`+#endif/* __aarch64__ \|\| __aarch64 */`
`340`	`357`	`#endif/* HAVE_GCC__SYNC_INT32_TAS */`
`341`	`358`	`#endif/* __arm__ \|\| __arm \|\| __aarch64__ \|\| __aarch64 */`
`342`	`359`

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