11// --------------------------------------------------------------------------------
22// pulse_stretch.sv
3+ // published as part of https://github.com/pConst/basic_verilog
34// Konstantin Pavlov, pavlovconst@gmail.com
45// --------------------------------------------------------------------------------
56
67// INFO --------------------------------------------------------------------------------
78// Pulse stretcher/extender module
8- // this implementftion uses a simple delay line or counter to stretch pulses
9- // WIDTH parameter sets output pulse width
10- // if you need variable output poulse width, see pulse_gen.sv module
9+ //
10+ // - this implementftion uses a simple delay line or counter to stretch pulses
11+ // - WIDTH parameter sets output pulse width
12+ // - if you need variable output poulse width, see pulse_gen.sv module
1113
1214
1315/* --- INSTANTIATION TEMPLATE BEGIN ---
@@ -24,6 +26,7 @@ pulse_stretch #(
2426
2527--- INSTANTIATION TEMPLATE END ---*/
2628
29+
2730module pulse_stretch # ( parameter
2831WIDTH = 8 ,
2932USE_CNTR = 0 // ==0 - stretcher is implemented on delay line
@@ -37,55 +40,57 @@ module pulse_stretch #( parameter
3740);
3841
3942
40- localparam CNTR_WIDTH = $clog2 (WIDTH )+ 1 ;
41-
42- generate
43-
44- if (WIDTH == 0 )begin
45- assign out= 0 ;
46-
47- end else if (WIDTH == 1 )begin
48- assign out= in;
49-
50- end else begin
51- if (USE_CNTR == '0 )begin
52- // delay line
43+ localparam CNTR_W = $clog2 (WIDTH + 1 );
5344
54- logic [WIDTH - 1 : 0 ] shifter= '0 ;
55- always_ff @ (posedge clk)begin
56- if (~ nrst )begin
57- shifter[WIDTH - 1 : 0 ]<= '0 ;
58- end else begin
59- // shifting
60- shifter[WIDTH - 1 : 0 ]<= { shifter[WIDTH - 2 : 0 ],in} ;
61- end // nrst
62- end // always
45+ generate
46+ // ==========================================================================
47+ if (WIDTH == 0 )begin
48+ assign out= 0 ;
6349
64- assign out= (shifter[WIDTH - 1 : 0 ]!= '0 );
50+ // ==========================================================================
51+ end else if (WIDTH == 1 )begin
52+ assign out= in;
6553
54+ // ==========================================================================
6655end else begin
67- // counter
68-
69- logic [CNTR_WIDTH - 1 : 0 ] cntr= '0 ;
70- always_ff @ (posedge clk)begin
71- if (~ nrst )begin
72- cntr[CNTR_WIDTH - 1 : 0 ]<= '0 ;
73- end else begin
74- if ( in )begin
75- // setting counter
76- cntr[CNTR_WIDTH - 1 : 0 ]<= CNTR_WIDTH ' (WIDTH );
77- end else if ( out )begin
78- // decrementing counter
79- cntr[CNTR_WIDTH - 1 : 0 ]<= cntr[CNTR_WIDTH - 1 : 0 ]- 1'b1 ;
80- end
81- end // nrst
82- end // always
83-
84- assign out= (cntr[CNTR_WIDTH - 1 : 0 ]!= '0 );
85-
86- end
87- end // if WIDTH
88- endgenerate
56+ if (USE_CNTR == '0 )begin
57+ // delay line
58+
59+ logic [WIDTH - 1 : 0 ] shifter= '0 ;
60+ always_ff @ (posedge clk)begin
61+ if (~ nrst )begin
62+ shifter[WIDTH - 1 : 0 ]<= '0 ;
63+ end else begin
64+ // shifting
65+ shifter[WIDTH - 1 : 0 ]<= { shifter[WIDTH - 2 : 0 ],in} ;
66+ end // nrst
67+ end // always
68+
69+ assign out= (shifter[WIDTH - 1 : 0 ]!= '0 );
70+
71+ end else begin
72+ // counter
73+
74+ logic [CNTR_W - 1 : 0 ] cntr= '0 ;
75+ always_ff @ (posedge clk)begin
76+ if (~ nrst )begin
77+ cntr[CNTR_W - 1 : 0 ]<= '0 ;
78+ end else begin
79+ if ( in )begin
80+ // setting counter
81+ cntr[CNTR_W - 1 : 0 ]<= CNTR_W ' (WIDTH );
82+ end else if ( out )begin
83+ // decrementing counter
84+ cntr[CNTR_W - 1 : 0 ]<= cntr[CNTR_W - 1 : 0 ]- 1'b1 ;
85+ end
86+ end // nrst
87+ end // always
88+
89+ assign out= (cntr[CNTR_W - 1 : 0 ]!= '0 );
90+
91+ end
92+ end // if WIDTH
93+ endgenerate
8994
9095
9196endmodule