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This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using high-swing cascode current mirror structures for the current source arrays.
muhammadaldacher/Analog-design-of-4-bit-current-steering-DACs
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This project shows the design & comparison of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using high-swing cascode current mirror structures for the current source arrays.
The standard deviation of the segmented DAC is smaller than that of the Binary DAC, giving better DNL performance.
==> Details on how to perform Monte Carlo Simulations:
https://github.com/muhammadaldacher/Analog-design-of-4-bit-current-steering-DACs/tree/master/Monte%20Carlo
My project on google drive:
https://drive.google.com/drive/folders/1W9ip4MpMZNf3IQsoFQkhgg6QaUya4Yp4
EE288 Lecture Notes:
https://drive.google.com/drive/folders/12Qqfw_TX1i7dvVVYXksaSdHV4gth1OD5
Videos on how to create VerilogA blocks for ADCs:https://drive.google.com/drive/folders/1GAobRzzFTkD6ywqSdDJUsO5g2C06hh_i
https://www.youtube.com/channel/UC7jwESeWKLcRbtxHwFS3A7Q/videos
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This project shows the design of two 4-bit current steering DACs, based on Binary and Segmented architectures at VDD=1.8V supply, using high-swing cascode current mirror structures for the current source arrays.