Copy AVX2 path to SSE4.2, adapt it as follows:

• Twice less than vector size threshold is 8
  • As a result, not engaged for 64-bit elements (disabled at compile time)
  • And only two variable shifts
• Sincemovemask output fits 16 bit (despite using 32-bit register), the mask with carry fits 32 bit
  • As a result, no tricky shift intrinsic needed, it will be good for x86 already
• Use BSF/BSR instead of TZCNT/LZCNT
  • Nonzero input always, albeit somewhat tricky to prove for BSR

Copy AVX2 path to AVX2 tail path, adapt it as follows:

• AND with tail mask before movemask
• Update_Carry with shifted_Msk_with_carry to take into account previous_Carry for tails smaller thann.

SSE4.2 benchmark results

These results are actually fake. AVX2 path is artificially disabled on an AVX2-capable CPU.
Also they suffer much from random variation.
Still they are useful enough to see that SSE4.2 path is indeed helpful.

I've highlighted the relevant results.