This commit extends the generic ASM API by adding the rest of theASM_{LOAD,STORE}[size]_REG_REG_OFFSET macros whenever applicable.The Viper int-indexed load/store code generator was changed to use thoseAPI functions if they are available, falling back to backend-specificimplementations if possible and ultimately to a generic implementation.Right now all backends except for x64 implement load16, load32, andstore32 operations (x64 only implements load16).Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

This commit lets the Thumb native code generator backend emit ARMv7-Mspecific opcodes for indexed load/store operations if possible.Now T3 opcode encodings are used if the generator backend is configuredto allow emitting ARMv7-M opcodes and if the (unsigned) scaled indexfits in 12 bits.  Or, in other words, LDR{B,H}.W and STR{B,H}.W opcodesare now emitted if possible.Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

This commit updates the existing specialised implementations forint-indexed 32-bit load and store operations, and adds a specialisedimplementation for int-indexed 16-bit load.The 32-bit operations relied on the fact that their applicability waslimited to a specific range, falling back on a generic implementationotherwise.  Introducing a single entry point for each int-indexedload/store operation size would break that assumption.  Now those twooperations contain fallback code to generate working code by themselvesinstead of raising an exception.The 16-bit operation instead simply did not have any range check, but itwas not exposed directly to the Viper emitter.  When a 16-bitint-indexed load entry point was introduced, the existing implementationwould fail when accessing memory outside its 0..255 halfwords range.  Aspecialised implementation is now present, performing fewer operationsthan the existing Viper emitter equivalent.Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

This commit removes redundant RV32 implementations of certainint-indexed code generation operations (32-bit load/store and 16-bitload).Those operations were already available as part of the native emitterAPI but were not exposed to the Viper code generator.  As part of theintroduction of more specialised load and store API calls toint-indexed Viper load/store generator bits, the existing native emitterimplementations are reused, thus making the Viper implementationsredundant.Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

This commit extends the range for int-indexed load/store opcodegenerators, making them emit correct code sequences for offsets thatspan more than 12 bits.This is necessary due to those generator bits being also used in theViper emitter, where it's more probable to reference offsets that cannot be embedded in the LDR/STR opcodes.Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

This commit performs a small refactoring on the Arm native emitter, byrenaming all but one instance of ASM_ARM_REG_R8 into REG_TEMP.ASM_ARM_REG_R8 is the temporary register used by the emitter whenoperations cannot overwrite the value of a particular register and someextra storage is needed.Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

This commit lets the test runner enumerate and run native tests if thefeature check fails but native tests were explicitly requested from thecommand line.The old behaviour would disable native tests anyway if the feature checkfailed, however this hid a bug in the x86 native emitter that would betriggered even during the feature check.  That meant the test suitewould pass on x86 even with a broken emitter, as those tests would havebeen skipped anyway.Now, if the user asks for native code it will get native code out of therunner no matter what.Co-authored-by: Damien George <damien@micropython.org>Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

This commit fixes CI test runs for the `nanbox` target, which werebroken by the unconditional native emitter code output changes in thetest runner.The `nanbox` configuration does not enable native emitters of any kind,and with a full test run that includes executing emitted native codethings would break when doing CI runs.This is worked around by introducing a common subset of tests that donot involve the native emitter, and a more comprehensive set of teststhat include both non-emitter and emitter tests.  The `nanbox` CI testrun will stop at the first subset, whilst other configurations will runthat and execute further tests.Function names have been kept the same for steps that involve nativecode, with the `nanbox` subset having another one.  This should nottrigger any breakage in existing CI configurations or external scripts.Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

This commit lets the native emitter backend extends the range of theBCCZ family of opcodes (BEQZ, BNEZ, BLTZ, BGEZ) from 12 bits to 18bits.The test suite contains some test files that, when compiled into nativecode, would require BCCZ jumps outside the (signed) 12 bits range.  Inthis case either the MicroPython interpreter or mpy-cross would raise anexception, not running the test when using the "--via-mpy --emit native"command line options with the test runner.This comes with a 3 bytes penalty on each forward jump, bringing thefootprint of those jumps to 6 bytes each, as a longer opcode sequencehas to be emitted to let jumps access a larger range.  However, this isslightly offset by the fact that backward jumps can be emitted with asingle opcode if the range is small enough (3 bytes for a 12-bitsoffset).Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

This commit lets the native emitter backend extends the range of theBCC family of opcodes (BALL, BANY, BBC, BBS, BEQ, BGE, BGEU, BLT,BLTU, BNALL, BNE, BNONE) from 8 bits to 18 bits.The test suite contains some test files that, when compiled into nativecode, would require BCC jumps outside the (signed) 8 bits range.  Inthis case either the MicroPython interpreter or mpy-cross would raise anexception, not running the test when using the "--via-mpy --emit native"command line options with the test runner.This comes with a 3 bytes penalty on each forward jump, bringing thefootprint of those jumps to 6 bytes each, as a longer opcode sequencehas to be emitted to let jumps access a larger range.  However, this isslightly offset by the fact that backward jumps can be emitted with asingle opcode if the range is small enough (8-bits offset).Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

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