target triple = "wasm32-unknown-unknown"define <2 x i128> @stest_f64i64() {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}

Legalizing node: t32: i128 = srl t50, Constant:i32<64>Analyzing result type: i128Expand integer result: t32: i128 = srl t50, Constant:i32<64>Assertion failed: ((Entry.first != 0) && "Operand isn't expanded"), function GetExpandedInteger, file LegalizeTypes.cpp, line 778.

lldb ./build_debug/bin/llc -- /Users/jjasmine/Developer/igalia/llvm-project/scratch/fp_load.ll -O3 -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128(lldb) target create "./build_debug/bin/llc"Current executable set to '/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc' (arm64).(lldb) settings set -- target.run-args  "/Users/jjasmine/Developer/igalia/llvm-project/scratch/fp_load.ll" "-O3" "-verify-machineinstrs" "-disable-wasm-fallthrough-return-opt" "-wasm-disable-explicit-locals" "-wasm-keep-registers" "-mattr=+simd128"(lldb) rProcess 73634 launched: '/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc' (arm64)Assertion failed: ((Entry.first != 0) && "Operand isn't expanded"), function GetExpandedInteger, file LegalizeTypes.cpp, line 778.Process 73634 stopped* thread #1, queue = 'com.apple.main-thread', stop reason = hit program assert    frame #4: 0x0000000102390108 llc`llvm::DAGTypeLegalizer::GetExpandedInteger(this=0x000000016fdfa5e0, Op=SDValue @ 0x000000016fdf8d80, Lo=0x000000016fdf96b0, Hi=0x000000016fdf96a0) at LegalizeTypes.cpp:778:3   775  void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo,   776                                            SDValue &Hi) {   777    std::pair<TableId, TableId> &Entry = ExpandedIntegers[getTableId(Op)];-> 778    assert((Entry.first != 0) && "Operand isn't expanded");   779    Lo = getSDValue(Entry.first);   780    Hi = getSDValue(Entry.second);   781  }Target 0: (llc) stopped.(lldb) p Op->dump()t202: v2i64,ch = load<(load (s128) from %fixed-stack.0)> t76, FrameIndex:i32<0>, undef:i32

ninja -C build_debug && ./build_debug/bin/llc reduced.ll -mtriple=wasm32-unknown-unknown -mattr=+simd128,+nontrapping-fptoint --print-after-all -print-changed -debug-only=isel,legalize-types -o - &> report.txt

*** IR Dump After Pre-ISel Intrinsic Lowering (pre-isel-intrinsic-lowering) ***; ModuleID = 'reduced.ll'source_filename = "reduced.ll"target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"target triple = "wasm32-unknown-unknown"define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}attributes #0 = { "target-features"="+simd128,+nontrapping-fptoint" }*** IR Dump After Expand large div/rem (expand-large-div-rem) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Expand fp (expand-fp) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Add prototypes to prototypes-less functions (wasm-add-missing-prototypes) ***; ModuleID = 'reduced.ll'source_filename = "reduced.ll"target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"target triple = "wasm32-unknown-unknown"define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}attributes #0 = { "target-features"="+simd128,+nontrapping-fptoint" }*** IR Dump After Lower @llvm.global_dtors via `__cxa_atexit` (lower-global-dtors) ***; ModuleID = 'reduced.ll'source_filename = "reduced.ll"target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"target triple = "wasm32-unknown-unknown"define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}attributes #0 = { "target-features"="+simd128,+nontrapping-fptoint" }*** IR Dump After WebAssembly Fix Function Bitcasts (wasm-fix-function-bitcasts) ***; ModuleID = 'reduced.ll'source_filename = "reduced.ll"target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"target triple = "wasm32-unknown-unknown"define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}attributes #0 = { "target-features"="+simd128,+nontrapping-fptoint" }*** IR Dump After WebAssembly Optimize Returned (wasm-optimize-returned) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Lower invoke and unwind, for unwindless code generators (lowerinvoke) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Remove unreachable blocks from the CFG (unreachableblockelim) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Expand indirectbr instructions (indirectbr-expand) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Module Verifier (verify) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Canonicalize natural loops (loop-simplify) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Merge contiguous icmps into a memcmp (mergeicmps) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Expand memcmp() to load/stores (expand-memcmp) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Lower Garbage Collection Instructions (gc-lowering) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Shadow Stack GC Lowering (shadow-stack-gc-lowering) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Remove unreachable blocks from the CFG (unreachableblockelim) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Constant Hoisting (consthoist) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Replace intrinsics with calls to vector library (replace-with-veclib) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Partially inline calls to library functions (partially-inline-libcalls) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Instrument function entry/exit with calls to e.g. mcount() (post inlining) (post-inline-ee-instrument) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Scalarize Masked Memory Intrinsics (scalarize-masked-mem-intrin) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Expand reduction intrinsics (expand-reductions) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After CodeGen Prepare (codegenprepare) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Lower invoke and unwind, for unwindless code generators (lowerinvoke) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Remove unreachable blocks from the CFG (unreachableblockelim) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After WebAssembly Reference Types Memory to Local (wasm-ref-type-mem2local) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Expand Atomic instructions (atomic-expand) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After WebAssembly Lower RefTypes Int-Ptr Conversions (wasm-lower-reftypes-intptr-conv) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After ObjC ARC contraction (objc-arc-contract) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Prepare callbr (callbrprepare) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Safe Stack instrumentation pass (safe-stack) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}*** IR Dump After Module Verifier (verify) ***define <2 x i128> @stest_f64i64() #0 {entry:  %conv = fptosi <2 x double> splat (double 0x7FF8000000000000) to <2 x i128>  ret <2 x i128> %conv}Legalizing node: t11: i32 = undefAnalyzing result type: i32Legal result typeLegally typed node: t11: i32 = undefLegalizing node: t5: f64 = ConstantFP<nan>Analyzing result type: f64Legal result typeLegally typed node: t5: f64 = ConstantFP<nan>Legalizing node: t15: v2f64 = splat_vector ConstantFP:f64<nan>Analyzing result type: v2f64Legal result typeAnalyzing operand: t5: f64 = ConstantFP<nan>Legal operandLegally typed node: t15: v2f64 = splat_vector ConstantFP:f64<nan>Legalizing node: t8: v2i128 = fp_to_sint t15Analyzing result type: v2i128Split node result: t8: v2i128 = fp_to_sint t15Legalizing node: t19: i32 = Constant<1>Analyzing result type: i32Legal result typeLegally typed node: t19: i32 = Constant<1>Legalizing node: t20: v1f64 = extract_subvector t15, Constant:i32<1>Analyzing result type: v1f64Widen node result 0: t20: v1f64 = extract_subvector t15, Constant:i32<1>Legalizing node: t22: v1i128 = fp_to_sint t20Analyzing result type: v1i128Scalarize node result 0: t22: v1i128 = fp_to_sint t20Legalizing node: t25: i128 = fp_to_sint ConstantFP:f64<nan>Analyzing result type: i128Expand integer result: t25: i128 = fp_to_sint ConstantFP:f64<nan>Legalizing node: t31: i32 = Constant<64>Analyzing result type: i32Legal result typeLegally typed node: t31: i32 = Constant<64>Legalizing node: t27: i32 = FrameIndex<0>Analyzing result type: i32Legal result typeLegally typed node: t27: i32 = FrameIndex<0>Legalizing node: t26: i32 = ExternalSymbol'__fixdfti'Analyzing result type: i32Legal result typeLegally typed node: t26: i32 = ExternalSymbol'__fixdfti'Legalizing node: t23: f64 = undefAnalyzing result type: f64Legal result typeLegally typed node: t23: f64 = undefLegalizing node: t24: v2f64 = BUILD_VECTOR ConstantFP:f64<nan>, undef:f64Analyzing result type: v2f64Legal result typeAnalyzing operand: t5: f64 = ConstantFP<nan>Legal operandAnalyzing operand: t23: f64 = undefLegal operandLegally typed node: t24: v2f64 = BUILD_VECTOR ConstantFP:f64<nan>, undef:f64Legalizing node: t17: i32 = Constant<0>Analyzing result type: i32Legal result typeLegally typed node: t17: i32 = Constant<0>Legalizing node: t18: v1f64 = extract_subvector t15, Constant:i32<0>Analyzing result type: v1f64Widen node result 0: t18: v1f64 = extract_subvector t15, Constant:i32<0>Legalizing node: t21: v1i128 = fp_to_sint t18Analyzing result type: v1i128Scalarize node result 0: t21: v1i128 = fp_to_sint t18Legalizing node: t3: i32 = Register %0Ignoring node resultsLegally typed node: t3: i32 = Register %0Legalizing node: t1: i32 = TargetConstant<0>Ignoring node resultsLegally typed node: t1: i32 = TargetConstant<0>Legalizing node: t2: i32 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>Analyzing result type: i32Legal result typeLegally typed node: t2: i32 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>Legalizing node: t0: ch,glue = EntryTokenAnalyzing result type: chLegal result typeAnalyzing result type: glueLegal result typeLegally typed node: t0: ch,glue = EntryTokenLegalizing node: t4: ch = CopyToReg t0, Register:i32 %0, t2Analyzing result type: chLegal result typeAnalyzing operand: t0: ch,glue = EntryTokenLegal operandAnalyzing operand: t2: i32 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>Legal operandLegally typed node: t4: ch = CopyToReg t0, Register:i32 %0, t2Legalizing node: t9: i32,ch = CopyFromReg t4, Register:i32 %0Analyzing result type: i32Legal result typeAnalyzing result type: chLegal result typeAnalyzing operand: t4: ch = CopyToReg t0, Register:i32 %0, t2Legal operandLegally typed node: t9: i32,ch = CopyFromReg t4, Register:i32 %0Legalizing node: t12: ch = store<(store (s256))> t4, t8, t9, undef:i32Analyzing result type: chLegal result typeAnalyzing operand: t4: ch = CopyToReg t0, Register:i32 %0, t2Legal operandAnalyzing operand: t8: v2i128 = fp_to_sint t15Split node operand: t12: ch = store<(store (s256))> t4, t8, t9, undef:i32Legalizing node: t35: i32 = Constant<16>Analyzing result type: i32Legal result typeLegally typed node: t35: i32 = Constant<16>Legalizing node: t36: i32 = add nuw t9, Constant:i32<16>Analyzing result type: i32Legal result typeAnalyzing operand: t9: i32,ch = CopyFromReg t4, Register:i32 %0Legal operandAnalyzing operand: t35: i32 = Constant<16>Legal operandLegally typed node: t36: i32 = add nuw t9, Constant:i32<16>Legalizing node: t37: ch = store<(store (s128) into unknown-address + 16, basealign 32)> t4, t22, t36, undef:i32Analyzing result type: chLegal result typeAnalyzing operand: t4: ch = CopyToReg t0, Register:i32 %0, t2Legal operandAnalyzing operand: t22: v1i128 = fp_to_sint t20Scalarize node operand 1: t37: ch = store<(store (s128) into unknown-address + 16, basealign 32)> t4, t22, t36, undef:i32Legalizing node: t39: ch = store<(store (s128) into unknown-address + 16, basealign 32)> t4, t25, t36, undef:i32Analyzing result type: chLegal result typeAnalyzing operand: t4: ch = CopyToReg t0, Register:i32 %0, t2Legal operandAnalyzing operand: t25: i128 = fp_to_sint ConstantFP:f64<nan>Expand integer operand: t39: ch = store<(store (s128) into unknown-address + 16, basealign 32)> t4, t25, t36, undef:i32Legalizing node: t41: i32 = Constant<8>Analyzing result type: i32Legal result typeLegally typed node: t41: i32 = Constant<8>Legalizing node: t42: i32 = add nuw t36, Constant:i32<8>Analyzing result type: i32Legal result typeAnalyzing operand: t36: i32 = add nuw t9, Constant:i32<16>Legal operandAnalyzing operand: t41: i32 = Constant<8>Legal operandLegally typed node: t42: i32 = add nuw t36, Constant:i32<8>Legalizing node: t34: ch = store<(store (s128), align 32)> t4, t21, t9, undef:i32Analyzing result type: chLegal result typeAnalyzing operand: t4: ch = CopyToReg t0, Register:i32 %0, t2Legal operandAnalyzing operand: t21: v1i128 = fp_to_sint t18Scalarize node operand 1: t34: ch = store<(store (s128), align 32)> t4, t21, t9, undef:i32Legalizing node: t45: ch = store<(store (s128), align 32)> t4, t25, t9, undef:i32Analyzing result type: chLegal result typeAnalyzing operand: t4: ch = CopyToReg t0, Register:i32 %0, t2Legal operandAnalyzing operand: t25: i128 = fp_to_sint ConstantFP:f64<nan>Expand integer operand: t45: ch = store<(store (s128), align 32)> t4, t25, t9, undef:i32Legalizing node: t47: i32 = add nuw t9, Constant:i32<8>Analyzing result type: i32Legal result typeAnalyzing operand: t9: i32,ch = CopyFromReg t4, Register:i32 %0Legal operandAnalyzing operand: t41: i32 = Constant<8>Legal operandLegally typed node: t47: i32 = add nuw t9, Constant:i32<8>Legalizing node: t28: ch = WebAssemblyISD::CALL t0, ExternalSymbol:i32'__fixdfti', FrameIndex:i32<0>, ConstantFP:f64<nan>Analyzing result type: chLegal result typeAnalyzing operand: t0: ch,glue = EntryTokenLegal operandAnalyzing operand: t26: i32 = ExternalSymbol'__fixdfti'Legal operandAnalyzing operand: t27: i32 = FrameIndex<0>Legal operandAnalyzing operand: t5: f64 = ConstantFP<nan>Legal operandLegally typed node: t28: ch = WebAssemblyISD::CALL t0, ExternalSymbol:i32'__fixdfti', FrameIndex:i32<0>, ConstantFP:f64<nan>Legalizing node: t29: i128,ch = load<(load (s128) from %stack.0)> t28, FrameIndex:i32<0>, undef:i32Analyzing result type: i128Expand integer result: t29: i128,ch = load<(load (s128) from %stack.0)> t28, FrameIndex:i32<0>, undef:i32Legalizing node: t50: v2i64,ch = load<(load (s128) from %stack.0)> t28, FrameIndex:i32<0>, undef:i32Analyzing result type: v2i64Legal result typeAnalyzing result type: chLegal result typeAnalyzing operand: t28: ch = WebAssemblyISD::CALL t0, ExternalSymbol:i32'__fixdfti', FrameIndex:i32<0>, ConstantFP:f64<nan>Legal operandAnalyzing operand: t27: i32 = FrameIndex<0>Legal operandAnalyzing operand: t11: i32 = undefLegal operandLegally typed node: t50: v2i64,ch = load<(load (s128) from %stack.0)> t28, FrameIndex:i32<0>, undef:i32Legalizing node: t32: i128 = srl t50, Constant:i32<64>Analyzing result type: i128Expand integer result: t32: i128 = srl t50, Constant:i32<64>Assertion failed: ((Entry.first != 0) && "Operand isn't expanded"), function GetExpandedInteger, file LegalizeTypes.cpp, line 778.PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.Stack dump:0.Program arguments: ./build_debug/bin/llc reduced.ll -mtriple=wasm32-unknown-unknown -mattr=+simd128,+nontrapping-fptoint -print-after-all -print-changed -debug-only=legalize-types -o -1.Running pass 'Function Pass Manager' on module 'reduced.ll'.2.Running pass 'WebAssembly Instruction Selection' on function '@stest_f64i64' #0 0x0000000102827280 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10273b280) #1 0x0000000102827878 PrintStackTraceSignalHandler(void*) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10273b878) #2 0x0000000102825278 llvm::sys::RunSignalHandlers() (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x102739278) #3 0x0000000102828b44 SignalHandler(int, __siginfo*, void*) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10273cb44) #4 0x0000000188644624 (/usr/lib/system/libsystem_platform.dylib+0x1804ac624) #5 0x000000018860a88c (/usr/lib/system/libsystem_pthread.dylib+0x18047288c) #6 0x0000000188513c60 (/usr/lib/system/libsystem_c.dylib+0x18037bc60) #7 0x0000000188512eec (/usr/lib/system/libsystem_c.dylib+0x18037aeec) #8 0x000000010247c108 llvm::DAGTypeLegalizer::GetExpandedInteger(llvm::SDValue, llvm::SDValue&, llvm::SDValue&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x102390108) #9 0x000000010246e7f8 llvm::DAGTypeLegalizer::ExpandShiftByConstant(llvm::SDNode*, llvm::APInt const&, llvm::SDValue&, llvm::SDValue&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x1023827f8)#10 0x0000000102467cc8 llvm::DAGTypeLegalizer::ExpandIntRes_Shift(llvm::SDNode*, llvm::SDValue&, llvm::SDValue&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10237bcc8)#11 0x000000010245b9c0 llvm::DAGTypeLegalizer::ExpandIntegerResult(llvm::SDNode*, unsigned int) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10236f9c0)#12 0x0000000102479ca8 llvm::DAGTypeLegalizer::run() (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10238dca8)#13 0x000000010247ea0c llvm::SelectionDAG::LegalizeTypes() (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x102392a0c)#14 0x0000000102605cc0 llvm::SelectionDAGISel::CodeGenAndEmitDAG() (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x102519cc0)#15 0x000000010260573c llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator_w_bits<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void, true, llvm::BasicBlock>, false, true>, llvm::ilist_iterator_w_bits<llvm::ilist_detail::node_options<llvm::Instruction, true, false, void, true, llvm::BasicBlock>, false, true>, bool&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10251973c)#16 0x00000001026050bc llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x1025190bc)#17 0x0000000102602de4 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x102516de4)#18 0x00000001002160cc (anonymous namespace)::WebAssemblyDAGToDAGISel::runOnMachineFunction(llvm::MachineFunction&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10012a0cc)#19 0x0000000102601780 llvm::SelectionDAGISelLegacy::runOnMachineFunction(llvm::MachineFunction&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x102515780)#20 0x0000000100d63828 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x100c77828)#21 0x000000010172b7c8 llvm::FPPassManager::runOnFunction(llvm::Function&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10163f7c8)#22 0x0000000101731f80 llvm::FPPassManager::runOnModule(llvm::Module&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x101645f80)#23 0x000000010172bfc0 (anonymous namespace)::MPPassManager::runOnModule(llvm::Module&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10163ffc0)#24 0x000000010172bb98 llvm::legacy::PassManagerImpl::run(llvm::Module&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10163fb98)#25 0x000000010173234c llvm::legacy::PassManager::run(llvm::Module&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x10164634c)#26 0x00000001000f0754 compileModule(char**, llvm::LLVMContext&) (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x100004754)#27 0x00000001000ee950 main (/Users/jjasmine/Developer/igalia/llvm-project/build_debug/bin/llc+0x100002950)#28 0x000000018826ab98