AMDGPU: Handle av imm pseudo in si-fix-sgpr-copies phi fold#149263

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arsenm merged 1 commit intomainfromusers/arsenm/amdgpu/handle-av-imm-pseudo-fix-sgpr-copies-phi-fold

Jul 18, 2025

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AMDGPU: Handle av imm pseudo in si-fix-sgpr-copies phi fold#149263

arsenm merged 1 commit intomainfromusers/arsenm/amdgpu/handle-av-imm-pseudo-fix-sgpr-copies-phi-fold

Jul 18, 2025

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arsenm commentedJul 17, 2025

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AMDGPU: Handle av imm pseudo in si-fix-sgpr-copies phi fold

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arsenm commentedJul 17, 2025

AMDGPU: Handle av imm pseudo in si-fix-sgpr-copies phi fold #149263 👈(View in Graphite)
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arsenm added the backend:AMDGPU label

Jul 17, 2025

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arsenm requested review fromjrbyrnes,srpande andcdevadas

July 17, 2025 06:21

arsenm marked this pull request as ready for review

July 17, 2025 06:21

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llvmbot commentedJul 17, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

Full diff:https://github.com/llvm/llvm-project/pull/149263.diff

2 Files Affected:

(modified) llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp (+1)
(modified) llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir (+56)

diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cppindex 9b5a46395695d..44d9ef5a0792e 100644--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp@@ -378,6 +378,7 @@ static bool isSafeToFoldImmIntoCopy(const MachineInstr *Copy,   default:     return false;   case AMDGPU::V_MOV_B32_e32:+  case AMDGPU::AV_MOV_B32_IMM_PSEUDO:     SMovOp = AMDGPU::S_MOV_B32;     break;   case AMDGPU::V_MOV_B64_PSEUDO:diff --git a/llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir b/llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mirindex c2c5340639a16..8145a1d7a2072 100644--- a/llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir+++ b/llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir@@ -167,3 +167,59 @@ body:             |     %1:sreg_32 = COPY %0     S_BRANCH %bb.2 ...++---++name:            phi_moveimm_av_pseudo_input+tracksRegLiveness: true+body:             |+  ; GCN-LABEL: name: phi_moveimm_av_pseudo_input+  ; GCN: bb.0:+  ; GCN-NEXT:   successors: %bb.1(0x80000000)+  ; GCN-NEXT:   liveins: $sgpr0, $sgpr1+  ; GCN-NEXT: {{  $}}+  ; GCN-NEXT:   [[AV_MOV_:%[0-9]+]]:vgpr_32 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec+  ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0+  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1+  ; GCN-NEXT: {{  $}}+  ; GCN-NEXT: bb.1:+  ; GCN-NEXT:   successors: %bb.2(0x80000000)+  ; GCN-NEXT: {{  $}}+  ; GCN-NEXT:   [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc+  ; GCN-NEXT:   S_BRANCH %bb.2+  ; GCN-NEXT: {{  $}}+  ; GCN-NEXT: bb.2:+  ; GCN-NEXT:   successors: %bb.3(0x80000000)+  ; GCN-NEXT: {{  $}}+  ; GCN-NEXT:   [[PHI:%[0-9]+]]:sreg_32 = PHI %5, %bb.3, [[S_ADD_U32_]], %bb.1+  ; GCN-NEXT:   S_BRANCH %bb.3+  ; GCN-NEXT: {{  $}}+  ; GCN-NEXT: bb.3:+  ; GCN-NEXT:   successors: %bb.2(0x80000000)+  ; GCN-NEXT: {{  $}}+  ; GCN-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0+  ; GCN-NEXT:   S_BRANCH %bb.2+  bb.0:+    successors: %bb.1+    liveins: $sgpr0, $sgpr1++    %0:vgpr_32 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec++    %4:sreg_32 = COPY $sgpr0+    %5:sreg_32 = COPY $sgpr1++  bb.1:+    successors: %bb.2+    %2:sreg_32 = S_ADD_U32 %4, %5, implicit-def $scc+    S_BRANCH %bb.2++  bb.2:+    successors: %bb.3+    %3:sreg_32 = PHI %1, %bb.3, %2, %bb.1+    S_BRANCH %bb.3++  bb.3:+    successors: %bb.2+    %1:sreg_32 = COPY %0+    S_BRANCH %bb.2+...